Continue to Site

# Open tranistors and voltage levels

Status
Not open for further replies.

#### Yarrow

##### Member level 2
tranistors

Hi

I have some difficulties understanding how transistors that are open at all times affect the voltage. If you see in the attachment, transistors M79(PMOS) and M66(NMOS) are always open. There is a DC current (2-3nA) going through the string given by M4. Furthermore M1 is open when M41 is closed and opposite. This makes the voltage between M1 and M41 (lets call it node N) to rise and fall.

So, what I dont understand is how M79(open) and M66(open) affect the voltage at node N. Can these open transistors be considered as "moscap"?

The thing I observed when including M66, the voltage level at node N increases when M41 is closed and M1 is open. What might be the cause of this? Increased resistance towards ground?

Based on simulation results, the use of M79 makes the voltage at node N to go high faster and thereby reduces delay. Anyone has any idea why?

Yarrow said:
If you see in the attachment, transistors M79(PMOS) and M66(NMOS) are always open. There is a DC current (2-3nA) going through the string given by M4. Furthermore M1 is open when M41 is closed and opposite. This makes the voltage between M1 and M41 (lets call it node N) to rise and fall.
The usage of the designations open and closed isn't consistent: For a switch or a circuit, open means high resistance, closed means low resistance. For a valve it's just the other way round.
As you designate the state of your pfet M79 (gate at gnd!) and nfet M66 as open, you use the valve designation method.

Yarrow said:
So, what I dont understand is how M79(open) and M66(open) affect the voltage at node N. Can these open transistors be considered as "moscap"?

The thing I observed when including M66, the voltage level at node N increases when M41 is closed and M1 is open. What might be the cause of this? Increased resistance towards ground?
If we agree to keep the above designation method, this behaviour is totally normal.

Yarrow said:
Based on simulation results, the use of M79 makes the voltage at node N to go high faster and thereby reduces delay. Anyone has any idea why?
Faster than which alternative? Faster than without M79? If so, I think your mosfets are asymmetric (their symbols suggest this), and you connected the pfets upside down. Still, I've got no explanation why the addition of M79 should accelerate the charging of node N. At least with the given w/l ratios, the charge storage of M79 isn't likely the reason.

### Yarrow

Points: 2
Tnx for the reply and sorry for the confusing designations..

Another thing I noticed was that, by dimentioning the M66 right, there will be a votage V>0, on the drain terminal of M66 which causes the voltage on node N to go higher then without M66 present when M41 is closed and M1 is open. This results in lower power consumption since node N is closer to Vdd..

I will have to look more into the PMOS transistor (M79), somhow the delay is reduced with the transistor present. I just have to find out why...

Yarrow said:
Another thing I noticed was that, by dimentioning the M66 right, there will be a voltage V>0 on the drain terminal of M66, which causes the voltage on node N to go higher than without M66 present when M41 is closed and M1 is open.
This is easily to be explained: 2 "valves" in series close better (i.e. in this case: show higher resistance) than 1 valve (or MOSFET) only.

Yarrow said:
I will have to look more into the PMOS transistor (M79), somhow the delay is reduced with the transistor present. I just have to find out why...
Did you try to exchange drain & source of your pfets (source closer to vdd than drain)? If these fets are actually asymmetric, the circuit should work better.

The devices are linear and symmentric, but I tried to flip the transistor so that the source is placed towards Vdd. There was no difference, as expected.

However I did a transient simulation, and I stand corrected when I said that the PMOS transistor (M79) reduces delay. Actually it increases the delay a bit, but contributed to a signal level increase compared to the situation when the transistor isnt present.

I attached the a graph that shows this. Orange is color is with M79, and purple is without M79. The lower graph is the output of an inverter. As you can see the output of the inverter, when M79 is included is much nicer then the case when M79 is excluded.

Based on simulation results, the case when M79 is included gives much better results when running Monte Carlo simulations at low temperatures (<40 degrees celcius)

I have been searching if this effect might be related to cascode current mirrors, but I cannot find a link that makes sence..

Yarrow said:
Orange color is with M79, and purple is without M79. The lower graph is the output of an inverter. As you can see the output of the inverter, when M79 is included is much nicer then the case when M79 is excluded.
...
I have been searching if this effect might be related to cascode current mirrors, but I cannot find a link that makes sence..
The rising edges you are showing on the upper graph are created when you close M41 and open M1 (still using your valve terminology). The effect could be explained, if the orange curve were with M66, the blue one without M66 (not M79). Same explanation as the first one I gave above, in this case.

Status
Not open for further replies.