joe2moon
Full Member level 5
leon2 vhdl download
1) Verilog source code
-- Sun releases open-source processor @03/21/2006
Sun Microsystems announced the release of open-source hardware and software specifications for its multi-threaded UltraSparc T1 (Niagara) processor, now called OpenSparc T1.
(**broken link removed**)
Sun released Verilog RTL code for the processor design, a verification suite and simulation models, an instruction set architecture specification, and the Solaris 10 operating system simulation images. (**broken link removed**)
Source browse:
**broken link removed**
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2) VHDL source code
LEON2 is a synthesisable VHDL model of a 32-bit processor compliant with the SPARC V8 architecture. (https://www.gaisler.com/products/leon2/leon.html)
LEON2 processor has the following features:
--------------------------------------------------
- SPARC V8 compliant integer unit with 5-stage pipeline
- Hardware multiply, divide and MAC units
- Interface to the Meiko FPU and custom co-processors
- Separate instruction and data cache (Hardvard architecture)
- Set-associative caches: 1 - 4 sets, 1 - 64 kbytes/set. Random, LRR or LRU replacement
- Data cache snooping
- AMBA-2.0 AHB and APB on-chip buses
- 8/16/32-bits memory controller for external PROM and SRAM
- 32-bits PC133 SDRAM controller
- On-chip peripherals such as uarts, timers, interrupt controller and 16-bit I/O port
- Advanced on-chip debug support unit and trace buffer
- Power-down mode
VHDL model:
https://www.gaisler.com/products/leon2/leon_down.html
--------------------------------------------------------------------------------------------
Should be helpful for
1) Beginner of Verilog/VHDL coding,
2) Understand the architecture of processor,
3) Look the design from the system view,
4) ....
ps:
*** Both processors have been tape-out to chip (ASIC or FPGA) and verified on the real system, not only pure academic projects. ***
1) Verilog source code
-- Sun releases open-source processor @03/21/2006
Sun Microsystems announced the release of open-source hardware and software specifications for its multi-threaded UltraSparc T1 (Niagara) processor, now called OpenSparc T1.
(**broken link removed**)
Sun released Verilog RTL code for the processor design, a verification suite and simulation models, an instruction set architecture specification, and the Solaris 10 operating system simulation images. (**broken link removed**)
Source browse:
**broken link removed**
-------------------------------------------------------------------
2) VHDL source code
LEON2 is a synthesisable VHDL model of a 32-bit processor compliant with the SPARC V8 architecture. (https://www.gaisler.com/products/leon2/leon.html)
LEON2 processor has the following features:
--------------------------------------------------
- SPARC V8 compliant integer unit with 5-stage pipeline
- Hardware multiply, divide and MAC units
- Interface to the Meiko FPU and custom co-processors
- Separate instruction and data cache (Hardvard architecture)
- Set-associative caches: 1 - 4 sets, 1 - 64 kbytes/set. Random, LRR or LRU replacement
- Data cache snooping
- AMBA-2.0 AHB and APB on-chip buses
- 8/16/32-bits memory controller for external PROM and SRAM
- 32-bits PC133 SDRAM controller
- On-chip peripherals such as uarts, timers, interrupt controller and 16-bit I/O port
- Advanced on-chip debug support unit and trace buffer
- Power-down mode
VHDL model:
https://www.gaisler.com/products/leon2/leon_down.html
--------------------------------------------------------------------------------------------
Should be helpful for
1) Beginner of Verilog/VHDL coding,
2) Understand the architecture of processor,
3) Look the design from the system view,
4) ....
ps:
*** Both processors have been tape-out to chip (ASIC or FPGA) and verified on the real system, not only pure academic projects. ***
