Opamp problems with the ratio and current mirror

[vhdl00]

attached is the opamp, I was having some problems( short channel)

1. the textbook and most people are talking about the ratio of M5 M7 and M3(M4) and M6. I was using bsim3 level 1 model without any problems, but transfer to cadence tools, with more sophiscated model, the ratio has to be changed. anymore has such experience, and any guideline?

2. regarding the current mirror, theoretically, with adjusting the size ration m10 and m5 and m7 and m8, we should be able to get the desired current, but in the simulation, to be able to get desired current, I still need readjust the size of m5,7, 8. or either use cascode to get desired current. any comments?

 

[sunking]

opamp problems again

1. with more sophiscated model is better. because the Vds is not the same. and dont worry about it, it only add a samll voffset
2. M10 M5 M7 M9 should change the same time for match.

 

[paulux]

Re: opamp problems again

Yes, sophisticated model gives more accurate results. Maybe your problem is due to too short channel length.

 

[vhdl00]

Re: opamp problems again

I was just thinking I was the only encounter such problems. just want to know how do you guys solve the problems like this. one more thing is like when I was transfer my desgin based on pspise(level 1), m5 m7 and m3(m4), m6 keep the ratio, either m7 or m6 will be out of sat region. i have to resize either one to make sure both on sat region. I found sometime a slight change of either m7 or m6 size, will make either one out of sat region. I was worrying any process variations(10%-30% during fab) would make my design not work. someone told me feedback could solve this problem? is it true?

thanks for any input

 

[paulux]

Re: opamp problems again

It's hard to say. It may depends on biasing current or biasing condition or operating point of transistor. Anyway, set your circuit to your operating condition to see if there is any problem. This is a usual & reasonable way.

 

[jutek]

Re: opamp problems again

what did you draw this schematic in??

regards

 

[wangwang96]

Re: opamp problems again

I think you can enlarge length of transistor to avoid short channel effect!

 

[tavakoli]

Re: opamp problems again

First of all your problem is kind of short channel effect (SCE) which could not be seen in simple modeling and by sure the simulation with LEVEL-49 parameters are more closer to reality.

now why these happends in a simple way the SCE means that Id in the mos depends not only on the Vgs but also on Vds as well. so in designing with short chanell devices you should take more care on Vds voltages in MOS devices and let them having more than a simple (Vgs-Vt) over them for better perfomance. as you may see by by increasing the vds voltage you get more better matching and output Res performance. although this is a good way but you will lose your headroom.

another way is increasing your chanell lengths to reduce the SCE effect but it would result in lower W/L s and also decreasing the high freq performance.

At last you could increase W and as a result you'll get better dc and low freq performance even with lower Vds. but the high frq performance is affected by this change (because of larger capacitances in the device).

None of the above ways are complete, but by combining them in an engineering ways you could get the best result for ur own perpose.

 

[montage2000]

opamp problems again

systematic offset is hard to avoid, because the voltage of gate of M10 and drain of M5 cannot be keep the same at all power supplies, so just simulate this ciucuit in the correct operation point to check.