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Current mirror doubt

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sneha rayala

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Is it because the vg of M2 can’t go up to support the same current ?
 

What range of R and Vgs is this condition true for M1?
What is the Vt value and Vgs value for M2 when this is true at 100uA?

Check your understanding of my interactive simulation and click on the switches or vary R with your mouse thumbwheel or edit on mobile.

Falstad model uses a default Vt= 1.5V and Beta= 0.02 which is easily changed >edit

In the saturation region, Ids = Beta * (Vgs - Vt)² / 2 then Ron = Vds/Ids

Then try to answer your own question and type it below mine.

1700686053871.png


Is there a mirror here? If not can you make one on my simulation? then file> export as a link > copy TinyURL and paste into your answer. for Bonus points ;)
 
Last edited:

No ideas yet?
--- Updated ---

if Ids= 100uA and Ids = Beta * (Vgs - Vt)² / 2 for M2 and Vt =1.5 , beta = 0.05 then Vgs= ?
Vgs = sqrt(2*100uA/0.05) + 1.5 = 1.56 V meaning M2 operates near the threshold and thus stays near voltage constant on Vds.

M2 stays around 1.56V/100uA= 15.6 kohm over this "wide range".

M1 will have this same resistance when Vgs M1=M2, meaning Point A must be at least 3.2V at 100uA.

If you increase the Vdd to 5V that supplies this CC=100uA, then Rd can increase to 33k easily as M1 Ron reduces to a low Ron and M2 Vds ≈ Vt stays fairly constant.

Notice all FET datasheets define Vgs(th) at some low current like 100 uA to 250 uA with Vgs=Vds. This is just above the Vt threshold with some high resistance value. The formula for Ids above tells you the current and thus the quadratic reduction in resistance so that this circuit between the CC on 100uA and the CV of M2 sensing M1's drain voltage results in a constant resistance for the sum of R & Ron {M1} over the wide range of R values from RdsOn up to at least the Rds=Vgs/Id where Vgs is just slightly above threshold.

OK? any questions?
--- Updated ---

in other words M1 varies its resistance with Vgs(M1) so the string can be sees as ;

at point A,
V = Vds1+Vds2 = Icc*{R+Ron(M1)}+Vds2

So mathematically as long if point A is at least twice Vt then R can vary over a wide range up to at least Vds/Ids.
So as Vds of M1 goes down and Vds on M2 goes up to maintain a constant Vgs2.

This results in constant resistance over this voltage range at point A to 0V in between a CC and a CV.
--- Updated ---

or rather
This results in constant resistance between a CC and a CV.
--- Updated ---

By the way (BTW) this is an example of a current mirror.

The left FET defines the current and the right side matches Vgs to produce the same current across Drain-Source.
 
Last edited:
Yes sir , now I got it ....Sorry for the late reply , thanks a lot for the efforts went in .. :)
 

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