# [SOLVED]Op-amp input capacitance simulation

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#### Junus2012 Hello

Kindly, How can I simulate the input capacitance of the operational amplifier ??

Regards

#### erikl

##### Super Moderator
Staff member Kindly, How can I simulate the input capacitance of the operational amplifier ??

Hello Junus,

this question has been asked so many times in this forum; why don't you use the search function?

In short: Put a unit current (1A) ac source at the input (or at any other node where you want to measure the total capacitance), then run an ac analysis. The voltage V at this node corresponds to its impedance Z=V/I=V/1 ≘ V .

• Junus2012

### Junus2012

Points: 2

#### Junus2012 Hello Erikl

may be you understand my question wrong, I dont want to simulate the input Impedance, I want the input capacitance of the CMOS Op-Amp

#### LvW Hello Erikl
may be you understand my question wrong, I dont want to simulate the input Impedance, I want the input capacitance of the CMOS Op-Amp

Junus - ask yourself: What is the impedance expression for a capacitance? If you are lucky the value of C is part of this expression.

• Junus2012

### Junus2012

Points: 2

#### Junus2012 if I am still thinking :wink::idea::idea: then the value of the impedance is in Ohm, I need the capacitive value in Farad

unless if you want me to do this XC = 1/2.Pi.Cin , then it is Ok for me now .

then please give me the circuit configuration for simulating it

many thanx

#### LvW if I am still thinking :wink::idea::idea: then the value of the impedance is in Ohm, I need the capacitive value in Farad
unless if you want me to do this XC = 1/2.Pi.Cin , then it is Ok for me now .
then please give me the circuit configuration for simulating it
many thanx

Junus - if you dont want to calculate by yourself you can, of course, let the simulation program perform this task.
In this case, use an ac voltage source of 1V so that the input current is i=1*wC and display the function i/w. Thus, you directly get the capacitance.

• Junus2012

### Junus2012

Points: 2

#### Junus2012 Hello

I was wondering about the circuit setup connection, I shorted the both inputs of the op-amp, is that right or I shold do the same connection of the bode blod setup ?

Thank you

#### erikl

##### Super Moderator
Staff member ... I shorted the both inputs of the op-amp, is that right or I shold do the same connection of the bode blod setup ?

Hello Junus,

don't short both inputs: you want to see the capacitance of each (or both) of the separated inputs, isn't it?
For this, use your application configuration setup - that's where you want to see its inputs' capacitance anyway, I guess.

If your application is open loop (e.g. comparator), use the Bode plot setup. Should you want to measure the inverting input's capacitance, instead of the huge RC (or LC) feedback, use the iprobe feedback element, if your tool offers it: this one allows for full DC and not any AC feedback. If you don't have this iprobe element, isolate the RC||LC feedback network by another huge R||L from the inverting input.

Buon natale, e in bocca al lupo!

#### Junus2012 Dear erikl

my application is for an open loop rather it is for amplification. I got the idea of shortening the inputs because In the closed loop the negative feedback will for the inputs to be equal and hence the difference is zero

the other interesting thing for me is that I used a resistor in series to make like low pass filter and I calculate the input capacitance at when the voltage drop by -3db from
Cin= 1/2.Pi.Rin.f(-3db) as seen in the image I attached.
I think this is a trust way to simulate or measure the input capacitance, otherwise I will get the complex input impedance (resistive and capacitive ) #### lamoun

##### Member level 5 Hello Junus.

If you would like to measure input capacitance with the RC method you describe, you will need to use a voltage pulse, not an AC current source.

As for which terminal to measure, I guess one terminal will be at a DC reference voltage and the other at the signal source, so that only one terminal is driven. Given that, you should only measure the capacitance of one terminal of the opamp. Don't forget to bias both terminals correctly, as in the real application, or else you will get faulty results.

#### Junus2012 Or even I measure the input capacitance from the filter concept I proposed but by connecting the Op-amp as a buffer. because I think that the negative fedback has no effect on the input or output capacitance of the amplifier.

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Hello lamoun,

Why must i use the transient test not the A.C test???,
with the a.c test i am sweeping the input frequency to simualte the filter , but I dont know what or how you do that with the transient simulation??

Hello Junus.

If you would like to measure input capacitance with the RC method you describe, you will need to use a voltage pulse, not an AC current source.

As for which terminal to measure, I guess one terminal will be at a DC reference voltage and the other at the signal source, so that only one terminal is driven. Given that, you should only measure the capacitance of one terminal of the opamp. Don't forget to bias both terminals correctly, as in the real application, or else you will get faulty results.

#### lamoun

##### Member level 5 Yes of course, my bad. AC analysis too, but with a voltage source not current source as in your schematic.

I guess you can even do it with the current source, but it will involve some extra calculations.

• Junus2012

### Junus2012

Points: 2

#### erikl

##### Super Moderator
Staff member ... I calculate the input capacitance at when the voltage drop by -3db from Cin= 1/2.Pi.Rin.f(-3db) as seen in the image I attached.
I think this is a trust way to simulate or measure the input capacitance, otherwise I will get the complex input impedance (resistive and capacitive )

Yes: at the -3dB point, the resistive and capacitive contributions to the total impedance are the same (because their susceptance values add orthogonally, which results in a total 1/√2 = -3dB value). So with a constant i injection and a v=i*z , i.e v~z plot - as suggested above - the capacitance's impedance share value C at this frequency f-3dB is equal to the resistive share value R(DC) at very low frequencies (where the AC curve is still horizontal), i.e. C=1/(2πf-3dB*R(DC)) .

Of course you can also inject a (unit size) constant v(ac) - as LvW suggested above - and plot i=i(f,Z) resp. i(f)=v/z(f) = 1/z(f). In this case use the f+3dB point of i(f) , so C = i(DC)/2πf+3dB .

Of course, both methods are valid only for a simple RC parallel connection model (which is a good approximation for most CMOS nodes). Such a test bench setup is completely meaningless, as it wouldn't represent any application (it's a connection for common mode rejection measurement).
Moreover: what do you think is the purpose of a resistor in series with an ideal current source? Would it change the current?
In German one would say: ;-)

• Junus2012

### Junus2012

Points: 2

#### Junus2012 I am sorry guys I mean to put in the picture a voltage source not a current source any way I think you got my idea of introducing like a low pass filter to detect the input capacitance

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#### erikl

##### Super Moderator
Staff member I am sorry guys I mean to put in the picture a voltage source not a current source
Ok. Next time you'd want to be a bit more thorough with your info. Such errors just create unnecessary answers. :-(

I think you got my idea of introducing like a low pass filter to detect the input capacitance
In this case you'd actually use a transient simulation of course. And your series resistance Rs should be small against the resistance Rp in parallel to the node to be measured: Rs « Rp .

#### Junus2012 Ok Sir, I will do it  But why want me to do the transient simulation ?, f(-3dB) is coming from the A.C analyses . I found this website regarding this methods

nd I also updated my pictures here Danke shon

Ok. Next time you'd want to be a bit more thorough with your info. Such errors just create unnecessary answers. :-(

In this case you'd actually use a transient simulation of course. And your series resistance Rs should be small against the resistance Rp in parallel to the node to be measured: Rs « Rp .

#### LvW Hi Junus, I think the whole thread - up to now - is a bit confusing since you didnt tell us what you really want.
OK- in your first posting you speak about the "input capacitance" of an opamp.
But remember: At first,the opamp has TWO inputs and - secondly - it can be (and normally is) operated with negative feedback.
Thus - what do you need? Input capacitance at which input in which configuration ?

#### FvM

##### Super Moderator
Staff member I'm missing some points in the discussion

- OP input impedance parameters must distinguish between differential and common mode
- depending on the OP internal structure it may be necessary to perform the measurement in a closed loop setup, at least with suitable DC bias

In a case of doubt, I would refer to the known internal OP design and consider which restrictions apply for the respective part

• Junus2012

### Junus2012

Points: 2

#### Junus2012 Hi Junus, I think the whole thread - up to now - is a bit confusing since you didn`t tell us what you really want.
OK- in your first posting you speak about the "input capacitance" of an opamp.
But remember: At first,the opamp has TWO inputs and - secondly - it can be (and normally is) operated with negative feedback.
Thus - what do you need? Input capacitance at which input in which configuration ?

Hello FvM
I am sorry if my post was a little confusing

Here I would tell you simply, I would have

1. Input Resistance Common mode/differential ...... (in my first post I didnt ask for this point but here)
2. Input Capacitance Common mode/differential

Does the input capacitor change with the negative feedback???

kindly if you assist your explanation with graph it will be easier for me to understand
thank you vermuch

#### FvM

##### Super Moderator
Staff member The therad is posted in the Analog IC Design Forum, thus I presume that you are talking about known OP structures. It would be reasonable to start with an input stage model that can clarify, if you need to analyze differential input capacitance seperately.

Simply assume an MOSFET differential pair with non-neglectable Cgs related to total input capacitance. You'll notice that the differential input capcitance effect on amplifier input capacitance will be mostly cancelled in closed loop, e.g. in the second post #16 schematic. The differential capacitance however appears in the loop gain with a resisitive feedback network, reduces phase margin and possibly causes instability. On the other hand, the differential input capacitance can cause feedforward to the output,

So instead of answering your question, I suggest to design a suitable OP input model and find the measurement circuit that is able to determin the model parameters,

• Junus2012

Points: 2