This can't work as here the current is determined by the much higher load resistor of 1 GOhm.
You better put V6 as a fixed voltage source (e.g. 5V) between drain and vdd (i.e. it creates vdd), no load resistor in between, sweep VG between 0 and 5V, and plot vdd divided by the nmos current. Use an ordinate's scale of Ohms, then you should see the nmos' resistance falling from an initially high value below the threshold voltage vth, after exceeding vth it should go down to several hundreds or tens of Ohms when increasing VG up to 5V.
Similar for the 2nd two images 9 & 10.PNG: With a load resistance of 1 GOhm you can't see the much lower transmission gate (TG) resistance. Remove R0 and connect vout to vdd/2. In your configuration the TG is always on (switch closed). Sweep the input voltage V0 from 0 to 5V and plot vdd/2 divided by the current through V0 (which equals the total current through the TG). Here again use an ordinate's scale of Ohms[/U], and you should see the low TG resistance (should look like a Vesuvius: peak near vdd/2 , s. e.g. any 4016|4066 data sheet).