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offset voltage of a clocked comparator

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Nov 7, 2008
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offset voltage


Anyone has idea on how to measure the input offset of a clocked comparator using LTSpice?


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offset comparator

stefannm said:

This little feedback simulation circuit worked well for me. See the link above.

In case you can't access it, the paper info is

A simulation method for accurately determining DC and dynamic offsets in comparators
Matthews, T.W. Heedley, P.L.

thx stefanm, but i still have the problem, for example, In the first test a difference in threshold voltage of 10mV was added to the M1-M2 input devices.

What changes i need to do in order the threshold difference of 10 mV between M2 and M1? I always think that threshold voltage is a fixed value that we can find in Spice Model. In my case BSIM3v3

clocked comparator offset simulation

hello stefanm,

I've just read through the article. In case of 2 inputs of comparator, how do you modify the DOTB? The practical example in that article having 4 input..


Added after 3 hours:

i'm having problem implementing the integrator and differential buffer. What i did was, i just took the universal op-amp model. it is similar to the picture in the my attachment. Is that ok??

comparator offset voltage + input

I was using spectre, so I was able to use ideal integrator using veriloga. I have attached my implementation of figure 2 (with some variation) from the paper. This picture shows the feedback path. The comparator was in a different schematic. My comparator was 2 input as well.

The same loop can be implemented using ideal opamps. Why don't you post your test bench and I will see if I can spot the issue.

measure offset voltage

hi stefanm,

I attached my test bench and the snapshot. You can simulate directly in LTSpice if you want. I've just simulated it and found 9mV offset (if i'm right). Is everything ok with my test bench?

clocked comparators

I don't have access to LTSpice. But I can give you some pointers.

A couple things:

1. I assume the output of your comparator is latched. If it is not, you need to add a latch to the output. Only the latched data should be used to drive the integrator. For example. during the sampling phase the clocked comparator outputs could be shorted to the inputs. This should not affect your loop.

2. Make sure you understand what S1 does. This switch is mostly for optimization of the simulation.

3. S3 can probably be replaced with an initial condition on the capacitor.

4. A reference voltage of 20m is a little small. I would expect it to be closer to the middle of your supply range. Of course, the offset voltage will change with your reference voltage. This change is a measure of the Common Mode Rejection.

Over all, it looks like you have the right idea. If your wave forms look like those in the paper, you are probably okay. The wave forms should look very much like they do in the paper. You need to be able to explain any variations if there are any. Remember that your offset voltage is the average of (Vf - Vin) of your comparator.
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