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fixing real life offset of an amplifer

yefj

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Hello, My simlation shown bellow has no offset voltage problem at all.
However in real life i am afraid that i would get a constant offset to the output instead of zero .
Am i correct?
I tried to plus many resistor in here and i cant see when can i put a potentiomater so in case i would have offset in real life then i would be able to fix it.
where can i connect a potentiometer (resistor in simulation) so could tune the offset ?
Thanks.

1695477705190.png

1695477688501.png
 
Assuming you are taking the output from U7, you can adjust the output DC level by changing the voltage on its '+' input. It probably wouldn't need much adjustment so the offset correction would only need to be small. I would suggest a 10K resistor from VCC to the top end of a 100 Ohm potentiometer and a 10K resistor from the bottom end to VEE with the wiper going to the non-inverting (+) pin on U7.

In theory you can do it for both stages but I doubt you would need more correction than the final stage could apply.

Note: lifting the + input from ground makes it a possible entry point for interference, you might benefit from adding a capacitor from that pin to ground to filter it out.

Brian.
 
Hi,

shown bellow has no offset voltage problem at all
It depends on the application whether "offset is a problem".
So you need to decide where your offset error limits are.

I had applications where "10uV of offset" was a problem and other projects where 1000 times that much was no problem.

Every OPAMP(circuit) causes offset, the one more the other less.
Every OPAMP comes with a datasheet, and every datasheet specifies the offset.
For the LT1028 the input offset voltage is specified to be less than 40uV. This is rather good.
You may compensate this initial offset with a pot, but you can´t compensate the offset drift with a pot!
An often made mistake: using a crappy OPAMP with the idea to compensate it´s offset, but forgetting about the drift.

Klaus
--- Updated ---

I would suggest a 10K resistor from VCC to the top end of a 100 Ohm potentiometer and a 10K resistor from the bottom end to VEE with the wiper going to the non-inverting (+) pin on U7.
I recommend to connect a fix 100R resistor between IN+ and GND,
10k pot between the supplies and an extra 10k from wiper to IN+.
This is less prone to errors and drift. (and wiper noise)
 
Last edited:
You can still find op amps with "null" pin(s) that allow some
bending of Vio with a trimpot or select resistors, as you say.
You just happen not to be using one.
 
From the datasheet :

1695487005579.png

Temp considerations :
1695487063420.png


There are T compensating techniques, as well as compound amplifier approaches,
lots of work by Analog Devices and the like. To get essentially zero offset. The compound
techniques take typically a fast opamp to handle the speed requirements, and a slow
one that has superb DC characteristics, an d mate them.




Regards, Dana.
 
Last edited:
I guess somebody didn't think the symbol deserved to have
all of its real pins represented. But if they were, somebody would
have had to do the work to make them functional in simulation,
I suppose.
 
The reason why offset adjustment pins are rarely used with LT1028 is that offset and offset drift over temperature are already wafer trimmed during fabrication. The achievable improvement by additional in-circuit trimming isn't so large.
 
The reason why offset adjustment pins are rarely used with LT1028 is that offset and offset drift over temperature are already wafer trimmed during fabrication. The achievable improvement by additional in-circuit trimming isn't so large.
Further, adding a trimming pot can actually make things worse due to the temperature coefficient of the pot.
 
  • The LT1028 is high-cost and high-performance OpAmp.
    The THT parts that were once >$30 and are effectively obsolete except from surplus guys.
  • There will always be cheaper choices with tradeoffs and better offset parts rated for 5 uV or 1 uV
  • It is good to understand the cost of Vos trimming is effective and increases with the time required to laser trim. It is a fascinating process done on the wafer that looks like a (silent) "Star Wars battle" with sparks flying all over the wafer from a high-power laser being deflected with precision during the measurement.
  • When searching in future, look for the button "similar" as choosing any part is always a tradeoff of cost, performance and availability.
  • Use the datasheet for offset trimming advice and simulate with a variable battery symbol. But if you know the input offset * DC Gain = Output offset, maybe you won't have to.
  • Make a list of Must Have specs for MHz, Vio, $/ch etc. separate from Nice-To-Have specs. Just as in any design the best parts meet all your Must-Have specs, just like all good designs meet all the absolute specs.
 
It is good to understand the cost of Vos trimming is effective and increases with the time required to laser trim. It is a fascinating process done on the wafer that looks like a (silent) "Star Wars battle" with sparks flying all over the wafer from a high-power laser being deflected with precision during the measurement.

Properly done, laser trim creates no sparks. The thin film resistor
material (a few hundred angstroms of NiCr or SiCr) is ablated and
entrains to the glass layers above and below, without damage to
oxide. This is key to passing HiRel die visual inspections.

There's a lot of tweaky process stuff involved. The oxide under the
trim resistors must create positive interference (not negative) to
maximize heat in the film, not elsewhere. This is optically inspected
(a specific color indicates a specific wavelength, which should be
half of the IR laser head wavelength).

Test is even "tweakier". The time to trim is a die level cost adder,
sure, but there's huge sunk cost in getting to a test solution that
delivers the Vio, every time. From die level pattern seeking to sub-
micron laser-head stepping, with a subset of fine testing per, and
by the way control your power level so your kerf-adjacent heat
affected region stays minuscule (no annealing). This also wraps
back around to oxide tuning, any detuning affects more of the
close in material still connected across. This leads to design of
compound trim structures, where "links" handle most of the range
and a tab or top hat patch delivers the sub-sub-LSB precision
(other aspects of the process, determining the accuracy after
burnin and lifetest - either per-packaged-part, or as a step in
qualifying the test*process combo for production.

We used to have a special room on the test floor with 4 big LTX
test stations, just for the parts that needed this kind of thing.
They do like to eat, and so do the test engineers who have to
stand it up and keep it up.

Now the point about 1uV, 5uV op amps is worth a look if Vio is
what matters, and bandwidth & spurious noises don't. There
are many rail-rail, "zero offset" chop amps out there which, if
you can tolerate a low frequency post filter, could be just the
ticket. Many in the 5V range, but some up to 40V, out there.
The op amp market is sliced pretty thin along lines of detail
parameter care-abouts and shopping is an exercise in itself.
 
Properly done, laser trim creates no sparks. The thin film resistor
material (a few hundred angstroms of NiCr or SiCr) is ablated and
entrains to the glass layers above and below, without damage to
oxide. This is key to passing HiRel die visual inspections.

There's a lot of tweaky process stuff involved. The oxide under the
trim resistors must create positive interference (not negative) to
maximize heat in the film, not elsewhere. This is optically inspected
(a specific color indicates a specific wavelength, which should be
half of the IR laser head wavelength).

Test is even "tweakier". The time to trim is a die level cost adder,
sure, but there's huge sunk cost in getting to a test solution that
delivers the Vio, every time. From die level pattern seeking to sub-
micron laser-head stepping, with a subset of fine testing per, and
by the way control your power level so your kerf-adjacent heat
affected region stays minuscule (no annealing). This also wraps
back around to oxide tuning, any detuning affects more of the
close in material still connected across. This leads to design of
compound trim structures, where "links" handle most of the range
and a tab or top hat patch delivers the sub-sub-LSB precision
(other aspects of the process, determining the accuracy after
burnin and lifetest - either per-packaged-part, or as a step in
qualifying the test*process combo for production.

We used to have a special room on the test floor with 4 big LTX
test stations, just for the parts that needed this kind of thing.
They do like to eat, and so do the test engineers who have to
stand it up and keep it up.

Now the point about 1uV, 5uV op amps is worth a look if Vio is
what matters, and bandwidth & spurious noises don't. There
are many rail-rail, "zero offset" chop amps out there which, if
you can tolerate a low frequency post filter, could be just the
ticket. Many in the 5V range, but some up to 40V, out there.
The op amp market is sliced pretty thin along lines of detail
parameter care-abouts and shopping is an exercise in itself.
I should have known better to limit the description of my observations to 40 yrs ago with thicker film devices being laser trimmed on ceramic at C-MAC in Sherbrooke.
 

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