Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Offset varation in different processes

Status
Not open for further replies.

gekk

Newbie level 4
Joined
Sep 7, 2007
Messages
6
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,321
i want to know offset varation in different process and w/L of input pair, thanks
 

savikx

Newbie level 5
Joined
Sep 24, 2007
Messages
8
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,283
Activity points
1,330
offset

generally, offset is inversely proportional to the input pair area W*L. Check ur technology file for more details.
 

gekk

Newbie level 4
Joined
Sep 7, 2007
Messages
6
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,321
offset

i want to know is ,have some estimate fomula about offset in defferent process?
such as in tsmc0.6 ,tsmc0.35 and tsmc 0.18
 

nassim_el85

Member level 4
Joined
Oct 26, 2006
Messages
77
Helped
6
Reputation
12
Reaction score
3
Trophy points
1,288
Activity points
1,747
offset

You can find some useful formulas in Gray book at part (3.5.6) and also in:

Marcel J.M. pelgrom, H.P.Tuinhout and M.Vertregt, "Transistor matching in analog CMOS applications" 1998 IEEE
 

lijianheng

Full Member level 2
Joined
Sep 29, 2006
Messages
125
Helped
13
Reputation
26
Reaction score
5
Trophy points
1,298
Activity points
1,826
Re: offset

Larger W*L and larger Vdsat can minimize offset.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top