daffo123
Junior Member level 2
Dear ALL.
I got some errors running elaboration after analyze with my code below in Synthesis
The error message as follows
Error: /work/ddr_ctrl.v:74: Clock expression must be one bit wide. (ELAB-367)
Error: /work/ddr_ctrl.v:74: Clock expression must be one bit wide. (ELAB-367)
Error: /work/ddr_ctrl.v:74: Clock expression must be one bit wide. (ELAB-367)
Error: /work/ddr_ctrl.v:74: Clock expression must be one bit wide. (ELAB-367)
*** Presto compilation terminated with 4 errors. ***
where, 74 represents 74th line of below attached code.
parameter PRE_END = 36'b100000000000000000000000000000000000;
And for your reference, my code is based on FSM.
Please let me know if you have any ideas to get rid of the error.
Thanks in advance
Best Regards.
// ----------------------------------------------------------------------
// DDR Controller
// ----------------------------------------------------------------------
module ddr_ctrl ( RESETb, sys_clk, ONE_MHZ, DDR_TEST,
BA, ADDR, CSb, WEb, RASb, CASb, DM, CLK, CLKb, CKE,
DQS_OUT, DQS_IN, DQS_OENb, DQ_OUT, DQ_IN, DQ_OENb,
FAIL, DONE );
input RESETb ;
input sys_clk ;
input ONE_MHZ ;
input DDR_TEST;
output [ 1:0] BA ;
output [11:0] ADDR ;
output CSb ;
output WEb ;
output RASb ;
output CASb ;
output [ 3:0] DM ;
output CLK ;
output CLKb ;
//output CKE ;
input CKE ;
output [ 3:0] DQS_OUT ;
input [ 3:0] DQS_IN ;
output DQS_OENb;
output [31:0] DQ_OUT ;
input [31:0] DQ_IN ;
output DQ_OENb ;
output FAIL;
output DONE ;
//-----------------------------------------------------------------
reg [35:0] cs, ns;
parameter INIT = 36'b000000000000000000000000000000000001;
parameter PRE_START = 36'b000000000000000000000000000000000010;
parameter TRP = 36'b000000000000000000000000000000000100;
parameter AUTO1 = 36'b000000000000000000000000000000001000;
parameter TRFC1 = 36'b000000000000000000000000000000010000;
parameter AUTO2 = 36'b000000000000000000000000000000100000;
parameter TRFC2 = 36'b000000000000000000000000000001000000;
parameter NMRS = 36'b000000000000000000000000000010000000;
parameter DUMMY1 = 36'b000000000000000000000000000100000000;
parameter EMRS = 36'b000000000000000000000000001000000000;
parameter IDLE = 36'b000000000000000000000000010000000000;
parameter AUTO3 = 36'b000000000000000000000000100000000000;
parameter ACT = 36'b000000000000000000000001000000000000;
parameter TRCD = 36'b000000000000000000000010000000000000;
parameter WRITE = 36'b000000000000000000000100000000000000;
parameter WR_0 = 36'b000000000000000000001000000000000000;
parameter WR_1 = 36'b000000000000000000010000000000000000;
parameter WR_2 = 36'b000000000000000000100000000000000000;
parameter WR_3 = 36'b000000000000000001000000000000000000;
parameter WR_4 = 36'b000000000000000010000000000000000000;
parameter WR_5 = 36'b000000000000000100000000000000000000;
parameter WR_6 = 36'b000000000000001000000000000000000000;
parameter WR_7 = 36'b000000000000010000000000000000000000;
parameter TWR = 36'b000000000000100000000000000000000000;
parameter READ = 36'b000000000001000000000000000000000000;
parameter CAS_LT1 = 36'b000000000010000000000000000000000000;
parameter CAS_LT2 = 36'b000000000100000000000000000000000000;
parameter RD_0 = 36'b000000001000000000000000000000000000;
parameter RD_1 = 36'b000000010000000000000000000000000000;
parameter RD_2 = 36'b000000100000000000000000000000000000;
parameter RD_3 = 36'b000001000000000000000000000000000000;
parameter RD_4 = 36'b000010000000000000000000000000000000;
parameter RD_5 = 36'b000100000000000000000000000000000000;
parameter RD_6 = 36'b001000000000000000000000000000000000;
parameter RD_7 = 36'b010000000000000000000000000000000000;
parameter PRE_END = 36'b100000000000000000000000000000000000;
wire cs_INIT = cs[ 0];
wire cs_PRE_START = cs[ 1];
wire cs_TRP = cs[ 2];
wire cs_AUTO1 = cs[ 3];
wire cs_TRFC1 = cs[ 4];
wire cs_AUTO2 = cs[ 5];
wire cs_TRFC2 = cs[ 6];
wire cs_NMRS = cs[ 7];
wire cs_DUMMY1 = cs[ 8];
wire cs_EMRS = cs[ 9];
wire cs_IDLE = cs[10];
wire cs_AUTO3 = cs[11];
wire cs_ACT = cs[12];
wire cs_TRCD = cs[13];
wire cs_WRITE = cs[14];
wire cs_WR_0 = cs[15];
wire cs_WR_1 = cs[16];
wire cs_WR_2 = cs[17];
wire cs_WR_3 = cs[18];
wire cs_WR_4 = cs[19];
wire cs_WR_5 = cs[20];
wire cs_WR_6 = cs[21];
wire cs_WR_7 = cs[22];
wire cs_TWR = cs[23];
wire cs_READ = cs[24];
wire cs_CAS_LT1 = cs[25];
wire cs_CAS_LT2 = cs[26];
wire cs_RD_0 = cs[27];
wire cs_RD_1 = cs[28];
wire cs_RD_2 = cs[29];
wire cs_RD_3 = cs[30];
wire cs_RD_4 = cs[31];
wire cs_RD_5 = cs[32];
wire cs_RD_6 = cs[33];
wire cs_RD_7 = cs[34];
wire cs_PRE_END = cs[35];
//-----------------------------------------------------------------
// Internal Signal Declaration
//-----------------------------------------------------------------
reg [13:0] row_addr;
//reg [ 8:0] col_addr;
reg [ 7:0] col_addr;
reg [ 2:0] wait_cnt;
reg write_en;
reg refresh_req;
reg FAIL_EVEN;
reg FAIL_ODD;
reg DONE_EVEN;
reg DONE_ODD;
wire page_end = (col_addr == 8'hf0);
wire wait_end = (&wait_cnt[2:0]);
wire test_end = (row_addr == 14'h3fff && col_addr == 8'hf0);
always @(negedge RESETb or posedge sys_clk)
if (!RESETb) write_en <= 1'b0;
else if (cs_ACT) write_en <= ~write_en;
always @(negedge RESETb or posedge sys_clk)
if (!RESETb) refresh_req <= 1'b0;
else if (cs_AUTO3) refresh_req <= 1'b0;
else if (cs_WR_7 | cs_RD_7) refresh_req <= 1'b1;
//-----------------------------------------------------------------
// FSM : Current State Generation
//-----------------------------------------------------------------
always @(negedge RESETb or posedge sys_clk)
if (!RESETb) cs <= INIT;
else cs <= ns;
//-----------------------------------------------------------------
// FSM : Next State Generation
//-----------------------------------------------------------------
//always @(*) begin
always @(cs_INIT or cs_PRE_START or cs_TRP or cs_AUTO1 or cs_TRFC1 or cs_AUTO2 or cs_TRFC2 or
cs_NMRS or cs_DUMMY1 or cs_EMRS or cs_IDLE or cs_ACT or cs_TRCD or cs_WRITE or cs_WR_0 or
cs_WR_1 or cs_WR_2 or cs_WR_3 or cs_WR_4 or cs_WR_5 or cs_WR_6 or cs_WR_7 or cs_TWR or cs_PRE_END or
cs_READ or cs_CAS_LT1 or cs_CAS_LT2 or cs_RD_0 or cs_RD_1 or cs_RD_2 or cs_RD_3 or cs_RD_4 or
cs_RD_5 or cs_RD_6 or cs_RD_7 or DDR_TEST or wait_end or test_end or refresh_req or write_en) begin
ns = INIT;
case (1'b1) // synopsys parallel_case full_case
cs_INIT : if (DDR_TEST) ns = PRE_START;
else ns = INIT;
cs_PRE_START : ns = TRP;
cs_TRP : if (wait_end) ns = AUTO1;
else ns = TRP;
cs_AUTO1 : ns = TRFC1;
cs_TRFC1 : if (wait_end) ns = AUTO2;
else ns = TRFC1;
cs_AUTO2 : ns = TRFC2;
cs_TRFC2 : if (wait_end) ns = NMRS;
else ns = TRFC2;
cs_NMRS : ns = DUMMY1;
cs_DUMMY1 : ns = EMRS;
cs_EMRS : ns = IDLE;
cs_IDLE : if (test_end) ns = IDLE;
else if (refresh_req) ns = AUTO3;
else ns = ACT;
cs_ACT : ns = TRCD;
cs_TRCD : if (wait_end & write_en) ns = WRITE;
else if (wait_end) ns = READ;
else ns = TRCD;
cs_WRITE : ns = WR_0;
cs_WR_0 : ns = WR_1;
cs_WR_1 : ns = WR_2;
cs_WR_2 : ns = WR_3;
cs_WR_3 : ns = WR_4;
cs_WR_4 : ns = WR_5;
cs_WR_5 : ns = WR_6;
cs_WR_6 : ns = WR_7;
cs_WR_7 : ns = TWR;
cs_TWR : if (wait_end) ns = PRE_END;
else ns = TWR;
cs_PRE_END : ns = IDLE;
cs_READ : ns = CAS_LT1;
cs_CAS_LT1 : ns = CAS_LT2;
cs_CAS_LT2 : ns = RD_0;
cs_RD_0 : ns = RD_1;
cs_RD_1 : ns = RD_2;
cs_RD_2 : ns = RD_3;
cs_RD_3 : ns = RD_4;
cs_RD_4 : ns = RD_5;
cs_RD_5 : ns = RD_6;
cs_RD_6 : ns = RD_7;
cs_RD_7 : ns = IDLE;
default : ns = INIT;
endcase
end
//-----------------------------------------------------------------
// WAIT COUNT Generation
//-----------------------------------------------------------------
always @(negedge RESETb or posedge sys_clk)
if (!RESETb) wait_cnt <= 3'b0;
else if (wait_end) wait_cnt <= 3'b0;
else if (cs_TRP | cs_TRFC1 | cs_TRFC2 | cs_TRCD | cs_TWR) wait_cnt <= wait_cnt + 1'b1;
//-----------------------------------------------------------------
// Output Signal Generation
//-----------------------------------------------------------------
assign RASb = ~(cs_PRE_START | cs_AUTO1 | cs_AUTO2 | cs_AUTO3 | cs_NMRS | cs_EMRS | cs_ACT | cs_PRE_END);
assign CASb = ~( cs_AUTO1 | cs_AUTO2 | cs_AUTO3 | cs_NMRS | cs_EMRS |
cs_WRITE | cs_READ);
assign WEb = ~(cs_PRE_START | cs_NMRS | cs_EMRS | cs_PRE_END | cs_WRITE);
assign CSb = ~(cs_PRE_START | cs_PRE_END | cs_NMRS | cs_EMRS);
wire A10 = (cs_PRE_START | cs_PRE_END | cs_WRITE | cs_READ);
wire WR_EVEN = (cs_WR_0 | cs_WR_2 | cs_WR_4 | cs_WR_6);
wire WR_ODD = (cs_WR_1 | cs_WR_3 | cs_WR_5 | cs_WR_7);
wire RD_EVEN = (cs_RD_0 | cs_RD_2 | cs_RD_4 | cs_RD_6);
wire RD_ODD = (cs_RD_1 | cs_RD_3 | cs_RD_5 | cs_RD_7);
assign DQ_OUT = (WR_EVEN) ? 32'haaaaaaaa :
(WR_ODD) ? 32'h55555555 : 32'b0;
assign DQ_OENb = ~(WR_EVEN | WR_ODD);
assign DQS_OUT = {~sys_clk, ~sys_clk, ~sys_clk, ~sys_clk};
assign DQS_OENb = ~(WR_EVEN | WR_ODD);
assign DM = (WR_EVEN | WR_ODD) ? 4'b0 : 4'hf;
//assign CSb = 1'b0;
//assign CKE = 1'b1;
assign FAIL = (FAIL_EVEN | FAIL_ODD);
assign DONE = (DONE_EVEN | DONE_ODD);
//-----------------------------------------------------------------
// Data input - Latch
//-----------------------------------------------------------------
reg [ 7:0] data_pos_latch0, data_pos_latch1, data_pos_latch2, data_pos_latch3;
reg [ 7:0] data_neg_latch0, data_neg_latch1, data_neg_latch2, data_neg_latch3;
wire [31:0] data_pos_latch_tmp = {data_pos_latch3, data_pos_latch2, data_pos_latch1, data_pos_latch0};
wire [31:0] data_neg_latch_tmp = {data_neg_latch3, data_neg_latch2, data_neg_latch1, data_neg_latch0};
//wire [31:0] data_latch_tmp = (data_pos_latch_tmp | data_neg_latch_tmp);
always @(negedge RESETb or posedge DQS_IN[0]) // Posedge DQS strobe signal for comparing data.
if (!RESETb) data_pos_latch0 <= 8'b0;
else data_pos_latch0 <= DQ_IN[7:0];
always @(negedge RESETb or posedge DQS_IN[1])
if (!RESETb) data_pos_latch1 <= 8'b0;
else data_pos_latch1 <= DQ_IN[15:8];
always @(negedge RESETb or posedge DQS_IN[2])
if (!RESETb) data_pos_latch2 <= 8'b0;
else data_pos_latch2 <= DQ_IN[23:16];
always @(negedge RESETb or posedge DQS_IN[3])
if (!RESETb) data_pos_latch3 <= 8'b0;
else data_pos_latch3 <= DQ_IN[31:24];
always @(negedge RESETb or negedge DQS_IN[0]) // Negedge DQS strobe signal for comparing data.
if (!RESETb) data_neg_latch0 <= 8'b0;
else data_neg_latch0 <= DQ_IN[7:0];
always @(negedge RESETb or negedge DQS_IN[1])
if (!RESETb) data_neg_latch1 <= 8'b0;
else data_neg_latch1 <= DQ_IN[15:8];
always @(negedge RESETb or negedge DQS_IN[2])
if (!RESETb) data_neg_latch2 <= 8'b0;
else data_neg_latch2 <= DQ_IN[23:16];
always @(negedge RESETb or negedge DQS_IN[3])
if (!RESETb) data_neg_latch3 <= 8'b0;
else data_neg_latch3 <= DQ_IN[31:24];
//-----------------------------------------------------------------
// Data Compare
//-----------------------------------------------------------------
`ifdef DATA_DELAY // ncverilog +access+rw ddr_ctrl_test.v +define+DATA_DELAY+FOR_TEST
reg [31:0] data_pos_latch;
reg [31:0] data_neg_latch;
always @(negedge RESETb or posedge DQS_IN)
if (!RESETb) data_pos_latch <= 32'b0;
else data_pos_latch <= data_pos_latch_tmp; //define more delays(reg) if needed
always @(negedge RESETb or negedge DQS_IN)
if (!RESETb) data_neg_latch <= 32'b0;
else data_neg_latch <= data_neg_latch_tmp; //define more delays(reg) if needed
always @(negedge RESETb or posedge DQS_IN)
if (!RESETb) FAIL_EVEN <= 1'b0;
else if (RD_EVEN == 1'b1 && data_latch == 32'haaaaaaaa) FAIL_EVEN <= 1'b0;
else if (RD_EVEN == 1'b1 && data_latch != 32'haaaaaaaa) FAIL_EVEN <= 1'b1;
always @(negedge RESETb or negedge DQS_IN)
if (!RESETb) FAIL_ODD <= 1'b0;
else if (RD_ODD == 1'b1 && data_latch == 32'haaaaaaaa) FAIL_ODD <= 1'b0;
else if (RD_ODD == 1'b1 && data_latch != 32'haaaaaaaa) FAIL_ODD <= 1'b1;
`else
always @(negedge RESETb or posedge DQS_IN)
if (!RESETb) FAIL_EVEN <= 1'b0;
else if (RD_EVEN == 1'b1 && data_pos_latch_tmp == 32'haaaaaaaa) FAIL_EVEN <= 1'b0;
else if (RD_EVEN == 1'b1 && data_pos_latch_tmp != 32'haaaaaaaa) FAIL_EVEN <= 1'b1;
always @(negedge RESETb or negedge DQS_IN)
if (!RESETb) FAIL_ODD <= 1'b0;
else if (RD_ODD == 1'b1 && data_neg_latch_tmp == 32'haaaaaaaa) FAIL_ODD <= 1'b0;
else if (RD_ODD == 1'b1 && data_neg_latch_tmp != 32'haaaaaaaa) FAIL_ODD <= 1'b1;
`endif
always @(negedge RESETb or posedge DQS_IN)
if (!RESETb) DONE_EVEN <= 1'b0;
// else if (data_pos_latch_tmp == 32'haaaaaaaa | data_pos_latch_tmp == 32'h55555555 && !FAIL && page_end) DONE_EVEN <= 1'b1;
else if (data_pos_latch_tmp == 32'haaaaaaaa | data_pos_latch_tmp == 32'h55555555 && !FAIL)
DONE_EVEN <= 1'b1;
else DONE_EVEN <= 1'b0;
always @(negedge RESETb or negedge DQS_IN)
if (!RESETb) DONE_ODD <= 1'b0;
// else if (data_neg_latch_tmp == 32'haaaaaaaa | data_neg_latch_tmp == 32'h55555555 && !FAIL && page_end)
DONE_ODD <= 1'b1;
else if (data_neg_latch_tmp == 32'haaaaaaaa | data_neg_latch_tmp == 32'h55555555 && !FAIL)
DONE_ODD <= 1'b1;
else DONE_ODD <= 1'b0;
//-----------------------------------------------------------------
// Address Generation
//-----------------------------------------------------------------
always @(negedge RESETb or posedge sys_clk)
if (!RESETb) row_addr <= 14'b0;
else if (page_end & cs_WR_7 ) row_addr <= row_addr + 1'b1;
always @(negedge RESETb or posedge sys_clk)
if (!RESETb) col_addr <= 8'b0;
else if (cs_WRITE) col_addr <= col_addr + 5'h10;
//Standard Mode Register
wire [2:0] BURST16 = 3'b100 ;
wire BURST_TYPE = 1'b0 ;
wire [2:0] CASLT3 = 3'b011 ;
wire [4:0] NORMAL = 5'b0;
//Extended Mode Register
wire [2:0] SELF_REFRESH_COVERAGE = 3'b0;
wire [1:0] A4_A3 = 2'b0;
wire [1:0] DRIVER_STRENGTH = 2'b0;
wire [4:0] EXTENDED = 5'b0;
assign BA = (cs_NMRS) ? 2'b0 :
(cs_EMRS) ? 2'b10 : row_addr[13:12];
assign ADDR = (cs_NMRS) ? {NORMAL, CASLT3, BURST_TYPE, BURST16} :
(cs_EMRS) ? {EXTENDED, DRIVER_STRENGTH, A4_A3, SELF_REFRESH_COVERAGE} :
(cs_ACT) ? row_addr[11:0] :
(cs_READ | cs_WRITE) ? {4'b0100, col_addr[7:0]} : {1'b0, A10, 10'b0} ;
endmodule
I got some errors running elaboration after analyze with my code below in Synthesis
The error message as follows
Error: /work/ddr_ctrl.v:74: Clock expression must be one bit wide. (ELAB-367)
Error: /work/ddr_ctrl.v:74: Clock expression must be one bit wide. (ELAB-367)
Error: /work/ddr_ctrl.v:74: Clock expression must be one bit wide. (ELAB-367)
Error: /work/ddr_ctrl.v:74: Clock expression must be one bit wide. (ELAB-367)
*** Presto compilation terminated with 4 errors. ***
where, 74 represents 74th line of below attached code.
parameter PRE_END = 36'b100000000000000000000000000000000000;
And for your reference, my code is based on FSM.
Please let me know if you have any ideas to get rid of the error.
Thanks in advance
Best Regards.
// ----------------------------------------------------------------------
// DDR Controller
// ----------------------------------------------------------------------
module ddr_ctrl ( RESETb, sys_clk, ONE_MHZ, DDR_TEST,
BA, ADDR, CSb, WEb, RASb, CASb, DM, CLK, CLKb, CKE,
DQS_OUT, DQS_IN, DQS_OENb, DQ_OUT, DQ_IN, DQ_OENb,
FAIL, DONE );
input RESETb ;
input sys_clk ;
input ONE_MHZ ;
input DDR_TEST;
output [ 1:0] BA ;
output [11:0] ADDR ;
output CSb ;
output WEb ;
output RASb ;
output CASb ;
output [ 3:0] DM ;
output CLK ;
output CLKb ;
//output CKE ;
input CKE ;
output [ 3:0] DQS_OUT ;
input [ 3:0] DQS_IN ;
output DQS_OENb;
output [31:0] DQ_OUT ;
input [31:0] DQ_IN ;
output DQ_OENb ;
output FAIL;
output DONE ;
//-----------------------------------------------------------------
reg [35:0] cs, ns;
parameter INIT = 36'b000000000000000000000000000000000001;
parameter PRE_START = 36'b000000000000000000000000000000000010;
parameter TRP = 36'b000000000000000000000000000000000100;
parameter AUTO1 = 36'b000000000000000000000000000000001000;
parameter TRFC1 = 36'b000000000000000000000000000000010000;
parameter AUTO2 = 36'b000000000000000000000000000000100000;
parameter TRFC2 = 36'b000000000000000000000000000001000000;
parameter NMRS = 36'b000000000000000000000000000010000000;
parameter DUMMY1 = 36'b000000000000000000000000000100000000;
parameter EMRS = 36'b000000000000000000000000001000000000;
parameter IDLE = 36'b000000000000000000000000010000000000;
parameter AUTO3 = 36'b000000000000000000000000100000000000;
parameter ACT = 36'b000000000000000000000001000000000000;
parameter TRCD = 36'b000000000000000000000010000000000000;
parameter WRITE = 36'b000000000000000000000100000000000000;
parameter WR_0 = 36'b000000000000000000001000000000000000;
parameter WR_1 = 36'b000000000000000000010000000000000000;
parameter WR_2 = 36'b000000000000000000100000000000000000;
parameter WR_3 = 36'b000000000000000001000000000000000000;
parameter WR_4 = 36'b000000000000000010000000000000000000;
parameter WR_5 = 36'b000000000000000100000000000000000000;
parameter WR_6 = 36'b000000000000001000000000000000000000;
parameter WR_7 = 36'b000000000000010000000000000000000000;
parameter TWR = 36'b000000000000100000000000000000000000;
parameter READ = 36'b000000000001000000000000000000000000;
parameter CAS_LT1 = 36'b000000000010000000000000000000000000;
parameter CAS_LT2 = 36'b000000000100000000000000000000000000;
parameter RD_0 = 36'b000000001000000000000000000000000000;
parameter RD_1 = 36'b000000010000000000000000000000000000;
parameter RD_2 = 36'b000000100000000000000000000000000000;
parameter RD_3 = 36'b000001000000000000000000000000000000;
parameter RD_4 = 36'b000010000000000000000000000000000000;
parameter RD_5 = 36'b000100000000000000000000000000000000;
parameter RD_6 = 36'b001000000000000000000000000000000000;
parameter RD_7 = 36'b010000000000000000000000000000000000;
parameter PRE_END = 36'b100000000000000000000000000000000000;
wire cs_INIT = cs[ 0];
wire cs_PRE_START = cs[ 1];
wire cs_TRP = cs[ 2];
wire cs_AUTO1 = cs[ 3];
wire cs_TRFC1 = cs[ 4];
wire cs_AUTO2 = cs[ 5];
wire cs_TRFC2 = cs[ 6];
wire cs_NMRS = cs[ 7];
wire cs_DUMMY1 = cs[ 8];
wire cs_EMRS = cs[ 9];
wire cs_IDLE = cs[10];
wire cs_AUTO3 = cs[11];
wire cs_ACT = cs[12];
wire cs_TRCD = cs[13];
wire cs_WRITE = cs[14];
wire cs_WR_0 = cs[15];
wire cs_WR_1 = cs[16];
wire cs_WR_2 = cs[17];
wire cs_WR_3 = cs[18];
wire cs_WR_4 = cs[19];
wire cs_WR_5 = cs[20];
wire cs_WR_6 = cs[21];
wire cs_WR_7 = cs[22];
wire cs_TWR = cs[23];
wire cs_READ = cs[24];
wire cs_CAS_LT1 = cs[25];
wire cs_CAS_LT2 = cs[26];
wire cs_RD_0 = cs[27];
wire cs_RD_1 = cs[28];
wire cs_RD_2 = cs[29];
wire cs_RD_3 = cs[30];
wire cs_RD_4 = cs[31];
wire cs_RD_5 = cs[32];
wire cs_RD_6 = cs[33];
wire cs_RD_7 = cs[34];
wire cs_PRE_END = cs[35];
//-----------------------------------------------------------------
// Internal Signal Declaration
//-----------------------------------------------------------------
reg [13:0] row_addr;
//reg [ 8:0] col_addr;
reg [ 7:0] col_addr;
reg [ 2:0] wait_cnt;
reg write_en;
reg refresh_req;
reg FAIL_EVEN;
reg FAIL_ODD;
reg DONE_EVEN;
reg DONE_ODD;
wire page_end = (col_addr == 8'hf0);
wire wait_end = (&wait_cnt[2:0]);
wire test_end = (row_addr == 14'h3fff && col_addr == 8'hf0);
always @(negedge RESETb or posedge sys_clk)
if (!RESETb) write_en <= 1'b0;
else if (cs_ACT) write_en <= ~write_en;
always @(negedge RESETb or posedge sys_clk)
if (!RESETb) refresh_req <= 1'b0;
else if (cs_AUTO3) refresh_req <= 1'b0;
else if (cs_WR_7 | cs_RD_7) refresh_req <= 1'b1;
//-----------------------------------------------------------------
// FSM : Current State Generation
//-----------------------------------------------------------------
always @(negedge RESETb or posedge sys_clk)
if (!RESETb) cs <= INIT;
else cs <= ns;
//-----------------------------------------------------------------
// FSM : Next State Generation
//-----------------------------------------------------------------
//always @(*) begin
always @(cs_INIT or cs_PRE_START or cs_TRP or cs_AUTO1 or cs_TRFC1 or cs_AUTO2 or cs_TRFC2 or
cs_NMRS or cs_DUMMY1 or cs_EMRS or cs_IDLE or cs_ACT or cs_TRCD or cs_WRITE or cs_WR_0 or
cs_WR_1 or cs_WR_2 or cs_WR_3 or cs_WR_4 or cs_WR_5 or cs_WR_6 or cs_WR_7 or cs_TWR or cs_PRE_END or
cs_READ or cs_CAS_LT1 or cs_CAS_LT2 or cs_RD_0 or cs_RD_1 or cs_RD_2 or cs_RD_3 or cs_RD_4 or
cs_RD_5 or cs_RD_6 or cs_RD_7 or DDR_TEST or wait_end or test_end or refresh_req or write_en) begin
ns = INIT;
case (1'b1) // synopsys parallel_case full_case
cs_INIT : if (DDR_TEST) ns = PRE_START;
else ns = INIT;
cs_PRE_START : ns = TRP;
cs_TRP : if (wait_end) ns = AUTO1;
else ns = TRP;
cs_AUTO1 : ns = TRFC1;
cs_TRFC1 : if (wait_end) ns = AUTO2;
else ns = TRFC1;
cs_AUTO2 : ns = TRFC2;
cs_TRFC2 : if (wait_end) ns = NMRS;
else ns = TRFC2;
cs_NMRS : ns = DUMMY1;
cs_DUMMY1 : ns = EMRS;
cs_EMRS : ns = IDLE;
cs_IDLE : if (test_end) ns = IDLE;
else if (refresh_req) ns = AUTO3;
else ns = ACT;
cs_ACT : ns = TRCD;
cs_TRCD : if (wait_end & write_en) ns = WRITE;
else if (wait_end) ns = READ;
else ns = TRCD;
cs_WRITE : ns = WR_0;
cs_WR_0 : ns = WR_1;
cs_WR_1 : ns = WR_2;
cs_WR_2 : ns = WR_3;
cs_WR_3 : ns = WR_4;
cs_WR_4 : ns = WR_5;
cs_WR_5 : ns = WR_6;
cs_WR_6 : ns = WR_7;
cs_WR_7 : ns = TWR;
cs_TWR : if (wait_end) ns = PRE_END;
else ns = TWR;
cs_PRE_END : ns = IDLE;
cs_READ : ns = CAS_LT1;
cs_CAS_LT1 : ns = CAS_LT2;
cs_CAS_LT2 : ns = RD_0;
cs_RD_0 : ns = RD_1;
cs_RD_1 : ns = RD_2;
cs_RD_2 : ns = RD_3;
cs_RD_3 : ns = RD_4;
cs_RD_4 : ns = RD_5;
cs_RD_5 : ns = RD_6;
cs_RD_6 : ns = RD_7;
cs_RD_7 : ns = IDLE;
default : ns = INIT;
endcase
end
//-----------------------------------------------------------------
// WAIT COUNT Generation
//-----------------------------------------------------------------
always @(negedge RESETb or posedge sys_clk)
if (!RESETb) wait_cnt <= 3'b0;
else if (wait_end) wait_cnt <= 3'b0;
else if (cs_TRP | cs_TRFC1 | cs_TRFC2 | cs_TRCD | cs_TWR) wait_cnt <= wait_cnt + 1'b1;
//-----------------------------------------------------------------
// Output Signal Generation
//-----------------------------------------------------------------
assign RASb = ~(cs_PRE_START | cs_AUTO1 | cs_AUTO2 | cs_AUTO3 | cs_NMRS | cs_EMRS | cs_ACT | cs_PRE_END);
assign CASb = ~( cs_AUTO1 | cs_AUTO2 | cs_AUTO3 | cs_NMRS | cs_EMRS |
cs_WRITE | cs_READ);
assign WEb = ~(cs_PRE_START | cs_NMRS | cs_EMRS | cs_PRE_END | cs_WRITE);
assign CSb = ~(cs_PRE_START | cs_PRE_END | cs_NMRS | cs_EMRS);
wire A10 = (cs_PRE_START | cs_PRE_END | cs_WRITE | cs_READ);
wire WR_EVEN = (cs_WR_0 | cs_WR_2 | cs_WR_4 | cs_WR_6);
wire WR_ODD = (cs_WR_1 | cs_WR_3 | cs_WR_5 | cs_WR_7);
wire RD_EVEN = (cs_RD_0 | cs_RD_2 | cs_RD_4 | cs_RD_6);
wire RD_ODD = (cs_RD_1 | cs_RD_3 | cs_RD_5 | cs_RD_7);
assign DQ_OUT = (WR_EVEN) ? 32'haaaaaaaa :
(WR_ODD) ? 32'h55555555 : 32'b0;
assign DQ_OENb = ~(WR_EVEN | WR_ODD);
assign DQS_OUT = {~sys_clk, ~sys_clk, ~sys_clk, ~sys_clk};
assign DQS_OENb = ~(WR_EVEN | WR_ODD);
assign DM = (WR_EVEN | WR_ODD) ? 4'b0 : 4'hf;
//assign CSb = 1'b0;
//assign CKE = 1'b1;
assign FAIL = (FAIL_EVEN | FAIL_ODD);
assign DONE = (DONE_EVEN | DONE_ODD);
//-----------------------------------------------------------------
// Data input - Latch
//-----------------------------------------------------------------
reg [ 7:0] data_pos_latch0, data_pos_latch1, data_pos_latch2, data_pos_latch3;
reg [ 7:0] data_neg_latch0, data_neg_latch1, data_neg_latch2, data_neg_latch3;
wire [31:0] data_pos_latch_tmp = {data_pos_latch3, data_pos_latch2, data_pos_latch1, data_pos_latch0};
wire [31:0] data_neg_latch_tmp = {data_neg_latch3, data_neg_latch2, data_neg_latch1, data_neg_latch0};
//wire [31:0] data_latch_tmp = (data_pos_latch_tmp | data_neg_latch_tmp);
always @(negedge RESETb or posedge DQS_IN[0]) // Posedge DQS strobe signal for comparing data.
if (!RESETb) data_pos_latch0 <= 8'b0;
else data_pos_latch0 <= DQ_IN[7:0];
always @(negedge RESETb or posedge DQS_IN[1])
if (!RESETb) data_pos_latch1 <= 8'b0;
else data_pos_latch1 <= DQ_IN[15:8];
always @(negedge RESETb or posedge DQS_IN[2])
if (!RESETb) data_pos_latch2 <= 8'b0;
else data_pos_latch2 <= DQ_IN[23:16];
always @(negedge RESETb or posedge DQS_IN[3])
if (!RESETb) data_pos_latch3 <= 8'b0;
else data_pos_latch3 <= DQ_IN[31:24];
always @(negedge RESETb or negedge DQS_IN[0]) // Negedge DQS strobe signal for comparing data.
if (!RESETb) data_neg_latch0 <= 8'b0;
else data_neg_latch0 <= DQ_IN[7:0];
always @(negedge RESETb or negedge DQS_IN[1])
if (!RESETb) data_neg_latch1 <= 8'b0;
else data_neg_latch1 <= DQ_IN[15:8];
always @(negedge RESETb or negedge DQS_IN[2])
if (!RESETb) data_neg_latch2 <= 8'b0;
else data_neg_latch2 <= DQ_IN[23:16];
always @(negedge RESETb or negedge DQS_IN[3])
if (!RESETb) data_neg_latch3 <= 8'b0;
else data_neg_latch3 <= DQ_IN[31:24];
//-----------------------------------------------------------------
// Data Compare
//-----------------------------------------------------------------
`ifdef DATA_DELAY // ncverilog +access+rw ddr_ctrl_test.v +define+DATA_DELAY+FOR_TEST
reg [31:0] data_pos_latch;
reg [31:0] data_neg_latch;
always @(negedge RESETb or posedge DQS_IN)
if (!RESETb) data_pos_latch <= 32'b0;
else data_pos_latch <= data_pos_latch_tmp; //define more delays(reg) if needed
always @(negedge RESETb or negedge DQS_IN)
if (!RESETb) data_neg_latch <= 32'b0;
else data_neg_latch <= data_neg_latch_tmp; //define more delays(reg) if needed
always @(negedge RESETb or posedge DQS_IN)
if (!RESETb) FAIL_EVEN <= 1'b0;
else if (RD_EVEN == 1'b1 && data_latch == 32'haaaaaaaa) FAIL_EVEN <= 1'b0;
else if (RD_EVEN == 1'b1 && data_latch != 32'haaaaaaaa) FAIL_EVEN <= 1'b1;
always @(negedge RESETb or negedge DQS_IN)
if (!RESETb) FAIL_ODD <= 1'b0;
else if (RD_ODD == 1'b1 && data_latch == 32'haaaaaaaa) FAIL_ODD <= 1'b0;
else if (RD_ODD == 1'b1 && data_latch != 32'haaaaaaaa) FAIL_ODD <= 1'b1;
`else
always @(negedge RESETb or posedge DQS_IN)
if (!RESETb) FAIL_EVEN <= 1'b0;
else if (RD_EVEN == 1'b1 && data_pos_latch_tmp == 32'haaaaaaaa) FAIL_EVEN <= 1'b0;
else if (RD_EVEN == 1'b1 && data_pos_latch_tmp != 32'haaaaaaaa) FAIL_EVEN <= 1'b1;
always @(negedge RESETb or negedge DQS_IN)
if (!RESETb) FAIL_ODD <= 1'b0;
else if (RD_ODD == 1'b1 && data_neg_latch_tmp == 32'haaaaaaaa) FAIL_ODD <= 1'b0;
else if (RD_ODD == 1'b1 && data_neg_latch_tmp != 32'haaaaaaaa) FAIL_ODD <= 1'b1;
`endif
always @(negedge RESETb or posedge DQS_IN)
if (!RESETb) DONE_EVEN <= 1'b0;
// else if (data_pos_latch_tmp == 32'haaaaaaaa | data_pos_latch_tmp == 32'h55555555 && !FAIL && page_end) DONE_EVEN <= 1'b1;
else if (data_pos_latch_tmp == 32'haaaaaaaa | data_pos_latch_tmp == 32'h55555555 && !FAIL)
DONE_EVEN <= 1'b1;
else DONE_EVEN <= 1'b0;
always @(negedge RESETb or negedge DQS_IN)
if (!RESETb) DONE_ODD <= 1'b0;
// else if (data_neg_latch_tmp == 32'haaaaaaaa | data_neg_latch_tmp == 32'h55555555 && !FAIL && page_end)
DONE_ODD <= 1'b1;
else if (data_neg_latch_tmp == 32'haaaaaaaa | data_neg_latch_tmp == 32'h55555555 && !FAIL)
DONE_ODD <= 1'b1;
else DONE_ODD <= 1'b0;
//-----------------------------------------------------------------
// Address Generation
//-----------------------------------------------------------------
always @(negedge RESETb or posedge sys_clk)
if (!RESETb) row_addr <= 14'b0;
else if (page_end & cs_WR_7 ) row_addr <= row_addr + 1'b1;
always @(negedge RESETb or posedge sys_clk)
if (!RESETb) col_addr <= 8'b0;
else if (cs_WRITE) col_addr <= col_addr + 5'h10;
//Standard Mode Register
wire [2:0] BURST16 = 3'b100 ;
wire BURST_TYPE = 1'b0 ;
wire [2:0] CASLT3 = 3'b011 ;
wire [4:0] NORMAL = 5'b0;
//Extended Mode Register
wire [2:0] SELF_REFRESH_COVERAGE = 3'b0;
wire [1:0] A4_A3 = 2'b0;
wire [1:0] DRIVER_STRENGTH = 2'b0;
wire [4:0] EXTENDED = 5'b0;
assign BA = (cs_NMRS) ? 2'b0 :
(cs_EMRS) ? 2'b10 : row_addr[13:12];
assign ADDR = (cs_NMRS) ? {NORMAL, CASLT3, BURST_TYPE, BURST16} :
(cs_EMRS) ? {EXTENDED, DRIVER_STRENGTH, A4_A3, SELF_REFRESH_COVERAGE} :
(cs_ACT) ? row_addr[11:0] :
(cs_READ | cs_WRITE) ? {4'b0100, col_addr[7:0]} : {1'b0, A10, 10'b0} ;
endmodule