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# numerically controlled oscillator (for SDR) in FPGA

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#### sssliz

##### Newbie level 6
hi!
we are doing a project on software defined radio. The digital down converter part in our project contains numerically controlled oscillator.
can you help me design nco using verilog plzzz..

You may use DDS IP Core provided by FPGA Vendor.

thnx...

your information was helpful.are those equation alone enough to design nco in verilog???

thnx...

are those equation alone enough to design nco in verilog???

What equations are you referring to?

those equation alone enough to design nco in verilog???
I guess, you are referring to the description of NCO operation in IP core manual?

A NCO is comprised of a phase accumulator, a sine table respectively generator algorithm and optionally modulation means. These are essentially simple operations and can be coded from the scratch. The vendor NCO IPs have several sine generation algorithms available to minimize resource usage.

If a simple sine table implementation doesn't satisfy your needs, it might be convenient to refer to existing NCO IP.

ravics

### ravics

Points: 2
thnx....FvM...

what does this statement "input [W_STEP-1:0] step; " in verilog mean??
where step is some input variable
and
parameter W_STEP = 24;

i got these statments from a program to execute nco...i am trying to figure out how that works.

It means what it says - a number with 24 bit width. The particular meaning of the step variable should be explained somewhere.

sssliz

### sssliz

Points: 2
input [W_STEP-1:0] step;

i understood that step is of 24 bit ,but what does [W_STEP-1:0] mean..?

what does [W_STEP-1:0] mean
W_STEP defines the word width of the variable step by defining the range for the bit index, [23:0] in this case. In Verilog terms it's a vector range specification. The direction is descending, as usual for numeric variables.

sssliz

Points: 2