Not operational: Clock Skew > Data Delay

[kask1984]

not operational: clock skew > data delay

hi every one ,
i am doing a project related to cdma .i wrote code for my system i am not able to meet timing requirement(according to compilation report).how to get rid of this waring.

"Warning: Circuit may not operate. Detected 8 non-operational path(s) clocked by clock "clk" with clock skew larger than data delay. See Compilation Report for details.'
i am using quartusII tool.
plz help me urgent.

 

[jarodz]

clock skew data delay

This is because you have combination logic in the clock network. FPGA can not fix this isuue automatically.

BR,
Jarod