Non integer generated clocks

[harpv]

I would like to generate a divided by 1.5 clock from a source clock. How do I create such a constraint for STA?

create_generated_clock command only has integer division support I believe.

 

[KlausST]

Hi,

best is to use a PLL.

Klaus

 

[jbeniston]

* 3 then / 2?

 

[harpv]

it has been generated by simple digital logic. No PLL involved.

((clk_by_2 (from clk posedge) | clk_by_2 (from clk negedge))

 

[D.A.(Tony)Stewart]

Once you define output requirements on frequency, voltage levels, and jitter, ( duty cycle will be 1/3) then you can define constraints on input duty cycle rise/fall time propagation delays and threshold.

If net Propagation time can be defined for symmetry then the realization is best for one edge to be most stable with supply and temperature changes.

 

[sharath666]

Try giving a generated clock on clk_by_2 (from clk posedge) and clk_by_2 (from clk negedge). Then give another create_generated_clock on the final clock specifying both above clocks as source_objects(You are allowed to specify more than a single source)..
I am not sure of this solution. But it is worth a try..Do let us know the solution in case you arrive at one..

 

[ads-ee]

Couldn't you use the -multiply_by and -divide_by at the same time? It's been awhile but I think that was the way you obtain fractional ratios for generated clock.