Generated clocks in a design

[alishetti07]

Hi,

Can anyone please explain the importance of a generated clock and its advantages.

Can't we have only the master clock in a design without using any generated clock?

Thanks

 

[KlausST]

Can't we have only the master clock in a design without using any generated clock?

Often it's the preferred solution, to use just one common clock
No divided clocks.
Just clock_enable.

Klaus

 

[dpaul]

I can reply from an FPGA point of view.

I use the command create_clock when the FPGA has input pins that carry-in clock signals in to the silicon (clock from the on-board osci, rgmii_rx_clk, and similar signals).
I use the command create_generated_clock for clocks which are outputs from the MMCM inside the FPGA.
This has worked for me so far.

It is like if you are putting a buffer, MMCM, PLL, anywhere within a clock's path, then the clock output of that path should be defined by the create_generated_clock command.

Correct me if I am wrong.

 

[ThisIsNotSam]

I can reply from an FPGA point of view.

I use the command create_clock when the FPGA has input pins that carry-in clock signals in to the silicon (clock from the on-board osci, rgmii_rx_clk, and similar signals).
I use the command create_generated_clock for clocks which are outputs from the MMCM inside the FPGA.
This has worked for me so far.

It is like if you are putting a buffer, MMCM, PLL, anywhere within a clock's path, then the clock output of that path should be defined by the create_generated_clock command.

Correct me if I am wrong.

this is generally the way it goes for ASICs too.

clock "sources" are defined with create_clock
modified versions of a clock are created with the create_generated_clock. could be a muxed clock, a divided clock, etc.

--- Updated Feb 24, 2022 ---

Hi,

Can anyone please explain the importance of a generated clock and its advantages.

Can't we have only the master clock in a design without using any generated clock?

Thanks

if your design has multiple clock domains, most likely you will have to use generated clocks. it's not about advantages, it is about necessity.

 

[morris_mano]

If you have divided down clock generated from main clock using some logic, then without generated clock constraint, the timing analysis tool may not know that the frequency of the generated clock is lower than the main clock. This will result in over constrained synthesis, where the logic using slower generated clock will still be timed at main clock frequency. In order to avoid this, generated clock definition with proper divisor or multiplier is needed to constraint synthesis appropriately.