non-ideal routing of differential pairs in multilayer board

[mijail]

I am having some doubts about differential pair routing; I'm hoping someone here can give me some answer / hint / heuristic / pointer about what to do.

The thing is, I have to route a number of differential pairs thru a long, constrained and fragmented space. I have 4 layers to use, the bottom one sporting a ground copper polygon (which does not extend further than the constrained routing area). The signals are expected to be <1 MHz. This is all in the process of reworking an old project, whose choices I am trying to understand/rethink.

So, what of the following would you think is worst, or best?

• to separate the traces of the differential pairs, even if that means running some of the traces parallel (same or different layer) to other separated differential traces?
• to try to keep traces from differential pairs together and in the same layer, even if that means making them go parallel to other differential pairs in other layers? (That would include things like stacking one trace from a differential pair over one trace from another differential pair in another layer)
• or to keep traces from differential pairs together but stacked, each trace in a different layer? (this would maximize horizontal separation between the various differential pairs)

My bet would be that the last option is the best one. It feels wrong, since I guess I am creating a big capacitor with those long parallel traces, which surely would not be good for a high speed design. But this isn't high speed, so that solution looks like the lesser evil.

I'm also thinking that the ground polygon will possibly be not a very good idea, since it will be affecting the impedance of the tracks in different ways, and being differential pairs anyway a ground plane is less important than the routing itself.

Any thoughts?

 

[keith1200rs]

It is tricky to be specific without a picture, but your preferred option sounds ok. Another thing so consider is running ground tracks between different pairs to minimise crosstalk if that could be a problem. Allowing signals to cross would create less crosstalk than allowing them to run parallel.

At 1MHz keeping the pairs parallel probably isn't that important but preventing crosstalk could be.

If you could post an image of the existing layouts with a doodle of the rerouting it may be possible to be more specific.

Keith

 

[mijail]

Re: non-ideal routing of differential pairs in multilayer bo

Thank you for your answer. Unfortunately, I don't have here the docs; on monday I will post a couple of screenshots to clarify the issue.

Regards.

 

[karesz]

Hi Mijail,
In first line is not the signal frequency so interesting but more the edge times! Most ppls cant believe it, but thats life
You can have some lower frequencies with edge times of i.e. 2nsec_as modern CMOS delivers it for us_ than if your timing need some clear rise edges = you must make impedance defined networks, maybe differential too...
In my opinion is the 3. version not the best, becouse you will have differently loaded lines _or you must correct the one (burried) hes impedances/parameters to the other_can you do it pls?
Remember pls, if your diff lines are symmetrical & the next one other line is min 3x of width of your diffline: maybe you dont need separation.
If you apply (its surly the better way) between diff-pairs: make pls often GND contact vias-in other case you will build a longly coupled (microstrip) trafo system, what I think you dont wish ...

For my point of wiev is the best solution to have the diff pairs on both outer sides!
So can you separate these wit GND & voltage planes too as the both internal layers
A burried diff line, called strip line technique, can give inpracticable line widths_ be care before placing/routing_
You must full & exact calculate your impedancies and check: is thes a real _typical_ internal FR4 thickness and cooper thickness & width by your PCB producer?!

I would never stock diff lines in different layers, only in pairs in different layers to route, but if possible only on the outside...
If their are longer parallel guided pairs in nearby relations; use the separation GND lines, but with enough often placed Vias to GND!

Btw; how long are your lines pls?
Good resultats!
K.

 

[FvM]

Re: non-ideal routing of differential pairs in multilayer bo

High speed differential pairs always means impedance matching (e.g. 100 ohm) as well, so there is effectively no problem with trace capacitances.

Differential pairs at low speed can mean a lot of different things. At least, it usually involve improved common mode rejection, but trace impedances, source and load termination, signal quality may vary over a wide range according to the respective design goals.

So as a first point, you should clarify what's the purpose for differential signalling in your design, what's the involved IO standard and signal level, if analog signal quality is implied, or just plain digital, e.g. RS-485.

 

[karesz]

Hallo,
...differently loaded lines _or you must correct the one (burried) hes impedances/parameters to the other_can you do it pls? ....

Sorry, I wished to write: trough parasitics differently influenced lines_...
K

 

[mijail]

Re: non-ideal routing of differential pairs in multilayer bo

Hi all,

Thank you for your suggestions, and sorry for the late answer. I have been reading a bit about differential pairs (I can't recommend enough this doc: https://www.speedingedge.com/PDF-Files/DiffSigDesign.pdf ), and have finally decided for the stacked configuration (or broadside, as seems to be called). I'll try to move the ground polygon to an internal layer, to have the traces of each pair symmetrical to it, and maybe add ground traces between the different pairs.

The traces are about 12 cm long.

The very little info I have about the system is that the signals are in the ballpark of RS422 (tens of KHz). I have also little freedom to change the original design, and no support to make any simulations or signal integrity analysis...

A couple of things to remember from what I have been reading (explained in the mentioned PDF):
The traces from a differential pair can be routed and treated separatedly; in fact it can be better not to put them too close (!). The real requisites are good terminations for the independent traces (which can be better not exactly matched!, to get a slight overshoot) and a sufficiently matched length, depending on the logic family. No need for matched impedances between the traces.

 

[karesz]

Hi Mijail,
Tnx for the good odf-file...
I must tell:
1,
be care with different impedancies from both (diff)lines!
This isnt practicable if you have much (Id tell; more as +/-5%)differencies...
OK with RS interface it will be not a problem, but with high-speed signaling & EMC-noises is others to handle!
2,
I can not agree with "in fact it can be better not to put them too close"_spaceing is beween two (diff)lines is practically between the copper with up to 2x, but you must it exactly callculate! Sorry, is not to say: better so and so... From field theory: the both fields are to work with others, thes means=>> exactly determined distance need too....
3,
For sufficient diff.-working against commonmode disturbances is a matched impedance needed between the both traces!
Good progress!
K.

Added after 5 minutes:

Other them; with your 12 cm line length & maybe ~5nsec edge times:you will "not much" problems have without defined impedances_because the reflection is after ca. 1.8 nsec, possibly enough below logic threshold & "befor comparing time"(in the first 30-45% of the pulse edge)...

 

[mijail]

Re: non-ideal routing of differential pairs in multilayer bo

I can not agree with "in fact it can be better not to put them too close"_spaceing is beween two (diff)lines is practically between the copper with up to 2x, but you must it exactly callculate! Sorry, is not to say: better so and so... From field theory: the both fields are to work with others, thes means=>> exactly determined distance need too....

Sorry, I am finding hard to understand you.

As you'll see in the PDF, there are reasons why the traces can have more problems when they are together. For example, the need and difficulty to keep their impedances, since they are affecting each other; so if they must get separated to avoid some obstacle, their impedances change and must be readjusted. In fact, the recommendation in the PDF is to use a rule of the type "not closer than"!

3,
For sufficient diff.-working against commonmode disturbances is a matched impedance needed between the both traces!

Another interesting point made in the PDF (and backed with simulations) is that "tight coupling between members of a differential pair does not protect them from crosstalk", since really the induced noise appears much stronger in one of the lines, no matter how you route them.
You'd need a twisted pair (not a couple of straight traces) to get the interference as common mode noise.

Of course, if there is a case where noise really affects equally both traces, then there is merit for the idea. For example, if the interference comes from a power plane with switching noise, I guess.

Regards.

 

[karesz]

...there are reasons why the traces can have more problems when they are together. For example, the need and difficulty to keep their impedances, since they are affecting each other; so if they must get separated to avoid some obstacle, their impedances change and must be readjusted. In fact, the recommendation in the PDF is to use a rule of the type "not closer than"!

Hi,
I wrote over that lines, some earlyer: you need to calculate it exactly!...

Sorry, I have much high-speed & highest density boards in my pratice; you must calculate a diff-line "As a diff-line" & not 2 individuals!!
Your design system/SW gives you the needed distances, ofcourse you can set other as the resultat is, than recalculate it & you will become other line withs/thickness or even material thickness too!
Thats life...
Maybe that some article means it others_or will miss interpreted_ but the physics will from that not change!

3,
For sufficient diff.-working against commonmode disturbances is a matched impedance needed between the both traces!

..."tight coupling between members of a differential pair does not protect them from crosstalk"...

...You'd need a twisted pair (not a couple of straight traces) to get the interference as common mode noise..

Of course, this isnt "commonmode effect" if only the one line is influenced!
For protect of that: shild/separate with a good HF-GND line between diff-pairs, but this was writen much time ago too...
I belive; I wrote it so practically word to word the same...
Otherwise an diffline with 50/100 Ohm impedance (or similar) has not so ligth corsstalk
Most are the "edge switching currents" as spikes a real problem...
K

Added after 14 minutes:

Apropos,
over distances: my "finest flex PCB" has had 16 micron line widths, believ me_their distances (between two lines of same diff construct) are calculated not for a half mm, it was less as 0.1mm!
All things are in life relative, than you have to see it as a "SYSTEM"...
K.

 

[mijail]

Re: non-ideal routing of differential pairs in multilayer bo

Sorry, I have much high-speed & highest density boards in my pratice;

I have very little experience , so I can't discuss that.
On the other hand, I must point out that the author of the PDF seems to be quite an authority (**broken link removed**: 3Com, Maxtor, NASA, wrote a number of books, does consulting and teaches on high speed design).
And, most importantly, he backs everything he says with the physical reasonings and even simulations, so he even debunks a number of rules-of-thumb.

you must calculate a diff-line "As a diff-line" & not 2 individuals!!
Your design system/SW gives you the needed distances, ofcourse you can set other as the resultat is, than recalculate it & you will become other line withs/thickness or even material thickness too!

The point is: although the software can help you, maybe the board won't be let you do what you want. That is my case, in which I simply CAN'T route the pairs together in the same plane - unless I switched manufacturing technologies or added layers to the PCB, which is out of the question.

So the interesting thing is: you CAN route the differential traces independently, and if they never get too close, their impedances will be independent! So, no need for recalculations and adjustments: less problems, less chances for errors, AND more flexible routing. So even autorouting would benefit from this.

 

[karesz]

Re: non-ideal routing of differential pairs in multilayer bo

Sorry, I have much high-speed & highest density boards in my pratice;

I have very little experience , so I can't discuss that...
...so he even debunks a number of rules-of-thumb.

Even: physics is not so easy to rebacking_but not npossible! I can respect the person, but I didnt read full hes script_ have too less time nowadys_ I know lot of design progress of my boards, but their do I know_& they are problemless in work over much years in high density racks & EMC disturbant environments too!

I wished only to tell some rules from exprienced persons & from me for you...

you must calculate a diff-line "As a diff-line" & not 2 individuals!!

...and if they never get too close, their impedances will be independent! So, no need for recalculations and adjustments: less problems, less chances for errors, AND more flexible routing. So even autorouting would benefit from this.

Sorry, you will be "waked up": latest as your board will be to test!...
Of course you need after all changing recalculations!
Did you checked pls, i.e., for exact impedancies of your burried part of diffline?:-(
Good luck & progress!
K.

 

[karesz]

Hi all,
hier is a good side for high speed diff line problems & calculations:...
High Speed & RF Deign_ PCB Matrix-FORUM
w*w.cad-hq.com/Downloads\Pruductvideos\PADS-HQ_imp.wmv
btw;
I have had practically the same SW to my calculations_sorry, its no more free to have (yet is price ~ 12K$...)
K.