Noise Margin b/w CMOS & ECL

[carrot]

Hi,

Which among CMOS and ECL is having better noise margin and why?

 

[v_c]

Noise Margin -- VOH VIH Margin VIL VOL Margin
TTL [5volt] 2.4v 2.0v 400mV 0.8v 0.5v 300mV
FCT [5volt] 2.5v 2.0v 500mV 0.8v 0.5v 300mV
BTL [5volt] 2.1v 1.62v 480mV 1.47v 1.1v 370mV
GTL [5volt] 1.5v 1.05v 450mV 0.95v 0.55v 400mV
CMOS [5volt] 4.9v 3.85v 1050mV 1.35v 0.1 1340mV
LVTTL [3volt] 2.4v 2.0v 400mV 0.8v 0.4v 400mV
LVCMOS [3volt] 2.8v 2.0v 800mV 0.8v 0.2v 600mV
CMOS [2.5v] 2.0v 1.7v 300mV 0.7v 0.4v 300mV
CMOS [1.8v] 1.35v 1.1v 250mV 0.66v 0.45v 210mV

Can't find the number for ECL -- and I don't have a textbook handy.
You might want to consult the datasheet for this. Look at the 100H or 10H parts for example.

Best regards,
v_c