Noise in fully differential op amp

[bhargava834]

auto zeroing to reduce flicker noise

I have designed a fully differential op amp in gain-boosting topology with 0.18µm technology, and i used ELDO simulator. I got input referred noise of 60nV/√Hz at 1KHz frequency, and 3nV/√Hz at higher frequencies.
So can any one suggest how to minimize the flicker noise present at low frequencies.

My specifications are DC gain: 115dB
UGB:1GHz
PD:4.5mW




Regards
Bhargav

 

[mengcy]

noise fully differential op-amp

you could list out the main noise source by the simulator.
increase the product of W*L of the noisy transistors.
usually,the input and the cascode transistors contribute most part of the noise.

 

[hock]

improve noise in op amps design

increase W/l of the input stage transsistor. make it atleast 10 times of what it is now and then see if the noise is redused. if not then chaek your telescopic stage.

hock

 

[bhargava834]

Thanks for the reply guys..

But when i increase the area of the transistors, which are contributing more for noise, the other parameters are changing. For example Phase margin is changing cosiderably(less than 0•).

Can u suggest any other efficient method to reduce the noise, without any changes in the op amp circuit??



----------
Bhargav

 

[diemilio]

Well, if you don't want to change anything in your opamp then there's only one solution left... adding more circuitry. If that's the approach you want to take then to reduce flicker noise you could use a chopper at the input of the amplifier to push the 1/f noise to higher frequencies...

This is not an easy task... but if you're up for the challenge, have the time to design it, and don't care about your power going a little bit up (I say a little because a well designed chopper should increase power consumption to much), I will say that's the best option.

Now, if you don't have to much time and don't have any experience with this kind of topology, I will really recommend that you redesign your opamp.

Regards,

diemilio

 

[bhargava834]

Thanks for your reply diemilio

I do not want to shift the noise from low frequencies to high frequencies(I mean in UGB range). I think that is not a good solution.

And redesigning may be a choice. So what are the precautions i should keep in mind to design for minimum noise???

There are some other techniques like auto zeroing, double sampled method to reduce the flicker noise. Do any one knows about these techniques???



Regards
Bhargav

 

[snafflekid]

the autozero is a type of chopper amplifier. It would be much simpler to increase your input stage size and adjust the frequency compensation if you run out of phase margin.

 

[jianjing526]

1/f noise always has a corner frequency that locates in 300k-1M in CMOS process. If you don't want to move it to higher frequency, then autozero is your choice. Treat it as a part of offset. Sample it in phase 1 and subtract it from the output in phase two. Besides,if the control sequence is properly set. 1/f noise will not have enough time to affect the output.

Good luck!

Jianjing526

 

[arunkumar446]

which mos transistors you are using as your input stage nmos or pmos
if you are using nmos try to design it with pmos, as pmos is sub surface device, it has less surface effect so less flicker noise effect.

 

[fanatic]

Thanks for your reply diemilio

I do not want to shift the noise from low frequencies to high frequencies(I mean in UGB range). I think that is not a good solution.

And redesigning may be a choice. So what are the precautions i should keep in mind to design for minimum noise???

There are some other techniques like auto zeroing, double sampled method to reduce the flicker noise. Do any one knows about these techniques???



Regards
Bhargav

hi, you can use pmos as inputstage
if you want improve niose performance, let us know that your op's structrue
and your noise summary which i mean is noise contribution

Added after 9 minutes:

Thanks for your reply diemilio

I do not want to shift the noise from low frequencies to high frequencies(I mean in UGB range). I think that is not a good solution.

And redesigning may be a choice. So what are the precautions i should keep in mind to design for minimum noise???

There are some other techniques like auto zeroing, double sampled method to reduce the flicker noise. Do any one knows about these techniques???



Regards
Bhargav

hi, you can use pmos as inputstage
if you want improve niose performance, let us know that your op's structrue
and your noise summary which i mean is noise contribution