mtwieg
Advanced Member level 6
Hi all, I'm designing low noise sample and hold circuits in umc_65 low leakage process, and for high density I want to use MOS capacitors for the sampling caps (50-100pF). However, I'm not sure if my noise and pnoise simulations are correctly accounting for the ESR of these caps, or other noise sources in them. The sample caps will be biased near 1.25 V, with only tens of millivolts of AC on them, so nonlinearity isn't a huge concern.
If I implement them with 1.2V low threshold nmos, then I see that the capacitors contribute a substantial amount of noise, specifically their igb (according to the noise report). Lowering the bias voltage to 1.0V reduces this greatly (though this isn't really an option in the final circuit). If I use 1.2V native nmos instead, I see the same effective capacitance, but less noise, and less leakage. However, I'm not convinced that the noise simulations account for ESR due to the poly and channel sheet resistances. If I do an AC simulation on the caps, then it shows no real impedance at all.
So if the models don't account for ESR, then what is this noise in the capacitors coming from? Why is it less in native transistors? Is there a way to force ESR to be modelled, or do I have to insert a parasitic resistor with an estimate of ESR?
If I implement them with 1.2V low threshold nmos, then I see that the capacitors contribute a substantial amount of noise, specifically their igb (according to the noise report). Lowering the bias voltage to 1.0V reduces this greatly (though this isn't really an option in the final circuit). If I use 1.2V native nmos instead, I see the same effective capacitance, but less noise, and less leakage. However, I'm not convinced that the noise simulations account for ESR due to the poly and channel sheet resistances. If I do an AC simulation on the caps, then it shows no real impedance at all.
So if the models don't account for ESR, then what is this noise in the capacitors coming from? Why is it less in native transistors? Is there a way to force ESR to be modelled, or do I have to insert a parasitic resistor with an estimate of ESR?