add wave sim:/counters_1/c
add wave sim:/counters_1/clr
add wave sim:/counters_1/q
force -freeze sim:/counters_1/c 1 0, 0 {50 ns} -r 100
force -freeze sim:/counters_1/clr 1 0 -cancel 10
run 100
force -freeze sim:/counters_1/clr 0 0 -cancel 10000
run 10000
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use work.all;
ENTITY proc IS
PORT( Data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
Reset, w : IN STD_LOGIC;
Clock : IN STD_LOGIC;
F, Rx, Ry : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
Done : BUFFER STD_LOGIC;
BusWires : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END proc;
ARCHITECTURE Behaviour OF proc IS
component dec2to4
Port (w : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
En : IN STD_LOGIC;
y : OUT STD_LOGIC_VECTOR(0 to 3));
end component;
component regn
generic (n:integer:=8);
Port ( R : in std_logic_vector(N-1 downto 0);
Rin : in std_logic;
Clock : in std_logic;
Q : out std_logic_vector(N-1 downto 0));
end component;
component trin
generic(n:integer:=8);
Port ( X : in std_logic_vector(N-1 downto 0);
E : in std_logic;
F : out std_logic_vector(N-1 downto 0));
end component;
component upcount
Port (clear,clock : IN STD_LOGIC;
Q : BUFFER STD_LOGIC_VECTOR(1 DOWNTO 0) );
end component;
SIGNAL Rin,Rout : STD_LOGIC_VECTOR(0 TO 3);
SIGNAL Clear, High, AddSub : STD_LOGIC;
SIGNAL Extern, Ain, Gin, Gout, FRin : STD_LOGIC;
SIGNAL Count : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL T, I, X, Y : STD_LOGIC_VECTOR(0 TO 3);
SIGNAL R0, R1, R2, R3 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL A, Sum, G : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL Func,FuncReg : STD_LOGIC_VECTOR(1 TO 6);
BEGIN
High <= '1';
Clear <= Reset OR Done OR (NOT w AND T(0));
Counter : upcount port map (Clear,Clock,Count );
decT : dec2to4 port map (Count, High, T );
Func <= F & Rx & Ry;
FRin <= w AND T(0);
Functionreg :regn GENERIC MAP (N => 6 )
PORT MAP ( Func, FRin, Clock, FuncReg );
decI : dec2to4 PORT MAP (FuncReg( 1 TO 2 ), High, I );
decX : dec2to4 PORT MAP (FuncReg( 3 TO 4 ), High, X );
decY : dec2to4 PORT MAP (FuncReg( 5 TO 6 ), High, Y );
Extern <= I(0) AND T(1);
Done <= ((I(0) OR I(1)) AND T(1)) OR ((I(2) OR I(3)) AND T(3));
Ain <= (I(2) OR I(3)) AND T(1);
Gin <= (I(2) OR I(3)) AND T(2);
Gout <= (I(2) OR I(3)) AND T(3);
AddSub <= I(3);
RegCntl:
FOR k IN 0 TO 3 GENERATE
Rin(k) <= ((I(0) OR I(1)) AND T(1) AND X(k)) OR
((I(2) OR I(3)) AND T(1) AND X(k));
Rout(k) <= (I(1) AND T(1) AND Y(k)) OR
((I(2) OR I(3)) AND ((T(1) AND X(k)) OR (T(2) AND Y(k))));
END GENERATE RegCntl;
tri_extern : trin PORT MAP (Data, Extern, BusWires );
reg0: regn PORT MAP (BusWires, Rin(0), Clock, R0);
reg1: regn PORT MAP (BusWires, Rin(1), Clock, R1);
reg2: regn PORT MAP (BusWires, Rin(2), Clock, R2);
reg3: regn PORT MAP (BusWires, Rin(3), Clock, R3);
tri0 : trin PORT MAP ( R0, Rout(0), BusWires );
tri1 : trin PORT MAP ( R1, Rout(1), BusWires );
tri2 : trin PORT MAP ( R2, Rout(2), BusWires );
tri3 : trin PORT MAP ( R3, Rout(3), BusWires );
regA : regn PORT MAP (BusWires, Ain, Clock, A );
alu :
WITH AddSub SELECT
Sum <= A + BusWires WHEN '0',
A - BusWires WHEN OTHERS;
regG : regn PORT MAP (Sum, Gin, Clock, G );
triG : trin PORT MAP (G, Gout, BusWires );
END Behaviour;
module test();
reg [7:0] Data;
reg Reset, w;
reg Clock;
reg [1:0] F, Rx, Ry;
wire Done;
wire [7:0] BusWires;
task command;
input [7:0] din;
input [5:0] cmd;
begin
@(posedge Clock);
@(negedge Clock);
Data <= din;
{F, Rx, Ry} <= cmd;
w <= 1;
@(negedge Clock);
w <= 0;
end
endtask // command
proc proc ( Data,
Reset, w,
Clock,
F, Rx, Ry,
Done,
BusWires);
initial begin
Data = 8'haa;
Reset = 1;
w = 0;
Clock = 0;
{F, Rx, Ry} = 8'b00_00_00;
#33 Reset = 0;
command(0,8'b00_00_00); //ld r0, 00
wait (Done);
command(1,8'b00_01_00); //ld r1, 01
wait (Done);
command(2,8'b00_10_00); //ld r2, 02
wait (Done);
command(3,8'b00_11_00); //ld r3, 03
wait (Done);
command(4,8'b01_01_00); //mov r1, r0
wait (Done);
command(4,8'b10_00_01); //add r1, r0
wait (Done);
command(4,8'b10_01_10); //add r2, r1
wait (Done);
command(4,8'b10_10_11); //add r3, r2
wait (Done);
command(4,8'b10_11_00); //add r3, r0
wait (Done);
#10 $finish;
end // initial begin
always #5 Clock = ~Clock;
endmodule // test
ibrary ieee;
use ieee.std_logic_1164.all;
use work.all;
entity test is
end test;
architecture behave of test is
component proc
PORT( Data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
Reset, w : IN STD_LOGIC;
Clock : IN STD_LOGIC;
F, Rx, Ry : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
Done : BUFFER STD_LOGIC;
BusWires : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0));
end component;
signal Data:std_logic_vector(7 downto 0);
signal Reset, w : std_logic;
signal Clock: std_logic := '0';
signal F, Rx, Ry : std_logic_vector(1 downto 0);
signal Done: std_logic;
signal BusWires: std_logic_vector(7 downto 0);
begin -- behave
Clock <= transport not Clock after 5 ns;
u1 : proc port map( Data,
Reset, w,
Clock,
F, Rx, Ry,
Done,
BusWires);
testbench: process
procedure command (
din : in std_logic_vector(7 downto 0);
cmd : in std_logic_vector(5 downto 0)) is
begin -- command
wait until Clock'event and Clock='1';
wait until Clock'event and Clock='0';
Data <= din;
F <= cmd(5 downto 4);
Rx <= cmd(3 downto 2);
Ry <= cmd(1 downto 0);
w <= '1';
wait until Clock'event and Clock='0';
w <= '0';
end command;
begin -- process testbench
Data <= "10101010";
Reset <= '1';
w <= '0';
Clock <= '0';
F <= "00";
Rx <= "00";
Ry <= "00";
wait for 33 ns;
Reset <= '0';
command("00000000","000000"); --ld r0, 00
wait until Done'event and Done='1';
command("00000001","000100"); --ld r1, 01
wait until Done'event and Done='1';
command("00000010","001000"); --ld r2, 02
wait until Done'event and Done='1';
command("00000011","001100"); --ld r3, 03
wait until Done'event and Done='1';
command("00000100", "010100"); --mov r1, r0
wait until Done'event and Done='1';
command("00000100", "100001"); --add r1, r0
wait until Done'event and Done='1';
command("00000100", "100110"); --add r2, r1
wait until Done'event and Done='1';
command("00000100", "101011"); --add r3, r2
wait until Done'event and Done='1';
command("00000100", "101100"); --add r3, r0
wait until Done'event and Done='1';
wait;
end process testbench;
end behave;
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity test is
end test;
architecture behave of test is
component proc
PORT( Data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
Reset, w : IN STD_LOGIC;
Clock : IN STD_LOGIC;
F, Rx, Ry : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
Done : BUFFER STD_LOGIC;
BusWires : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0));
end component;
signal Data:std_logic_vector(7 downto 0);
signal Reset, w : std_logic;
signal Clock: std_logic := '0';
signal F, Rx, Ry : std_logic_vector(1 downto 0);
signal Done: std_logic;
signal BusWires: std_logic_vector(7 downto 0);
begin -- behave
Clock <= transport not Clock after 5 ns;
u1 : proc port map( Data,
Reset, w,
Clock,
F, Rx, Ry,
Done,
BusWires);
testbench: process
procedure command (
din : in std_logic_vector(7 downto 0);
cmd : in std_logic_vector(5 downto 0)) is
begin -- command
wait until Clock'event and Clock='1';
wait until Clock'event and Clock='0';
Data <= din;
F <= cmd(5 downto 4);
Rx <= cmd(3 downto 2);
Ry <= cmd(1 downto 0);
w <= '1';
wait until Clock'event and Clock='0';
w <= '0';
end command;
begin -- process testbench
Data <= "10101010";
Reset <= '1';
w <= '0';
F <= "00";
Rx <= "00";
Ry <= "00";
wait for 33 ns;
Reset <= '0';
command("00000000","000000"); --ld r0, 00
wait until Done='0';
command("00000001","000100"); --ld r1, 01
wait until Done='0';
command("00000010","001000"); --ld r2, 02
wait until Done='0';
command("00000011","001100"); --ld r3, 03
wait until Done='0';
command("00000100", "010100"); --mov r1, r0
wait until Done='0';
command("00000100", "100001"); --add r1, r0
wait until Done='0';
command("00000100", "100110"); --add r2, r1
wait until Done='0';
command("00000100", "101011"); --add r3, r2
wait until Done='0';
command("00000100", "101100"); --add r3, r0
wait until Done='0';
wait;
end process testbench;
end behave;
<<project.vhd>>
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use work.all;
ENTITY proc IS
PORT( Data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
Reset, w : IN STD_LOGIC;
Clock : IN STD_LOGIC;
F, Rx, Ry : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
Done : BUFFER STD_LOGIC;
BusWires : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END proc;
ARCHITECTURE Behaviour OF proc IS
component dec2to4
Port (w : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
En : IN STD_LOGIC;
y : OUT STD_LOGIC_VECTOR(0 to 3));
end component;
component regn
generic (n:integer:=8);
Port ( R : in std_logic_vector(N-1 downto 0);
Rin : in std_logic;
Clock : in std_logic;
Q : out std_logic_vector(N-1 downto 0));
end component;
component trin
generic(n:integer:=8);
Port ( X : in std_logic_vector(N-1 downto 0);
E : in std_logic;
F : out std_logic_vector(N-1 downto 0));
end component;
component upcount
Port (clear,clock : IN STD_LOGIC;
Q : BUFFER STD_LOGIC_VECTOR(1 DOWNTO 0) );
end component;
SIGNAL Rin,Rout : STD_LOGIC_VECTOR(0 TO 3);
SIGNAL Clear, High, AddSub : STD_LOGIC;
SIGNAL Extern, Ain, Gin, Gout, FRin : STD_LOGIC;
SIGNAL Count : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL T, I, X, Y : STD_LOGIC_VECTOR(0 TO 3);
SIGNAL R0, R1, R2, R3 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL A, Sum, G : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL Func,FuncReg : STD_LOGIC_VECTOR(1 TO 6);
BEGIN
High <= '1';
Clear <= Reset OR Done OR (NOT w AND T(0));
Counter : upcount port map (Clear,Clock,Count );
decT : dec2to4 port map (Count, High, T );
Func <= F & Rx & Ry;
FRin <= w AND T(0);
Functionreg :regn GENERIC MAP (N => 6 )
PORT MAP ( Func, FRin, Clock, FuncReg );
decI : dec2to4 PORT MAP (FuncReg( 1 TO 2 ), High, I );
decX : dec2to4 PORT MAP (FuncReg( 3 TO 4 ), High, X );
decY : dec2to4 PORT MAP (FuncReg( 5 TO 6 ), High, Y );
Extern <= I(0) AND T(1);
Done <= ((I(0) OR I(1)) AND T(1)) OR ((I(2) OR I(3)) AND T(3));
Ain <= (I(2) OR I(3)) AND T(1);
Gin <= (I(2) OR I(3)) AND T(2);
Gout <= (I(2) OR I(3)) AND T(3);
AddSub <= I(3);
RegCntl:
FOR k IN 0 TO 3 GENERATE
Rin(k) <= ((I(0) OR I(1)) AND T(1) AND X(k)) OR
((I(2) OR I(3)) AND T(1) AND X(k));
Rout(k) <= (I(1) AND T(1) AND Y(k)) OR
((I(2) OR I(3)) AND ((T(1) AND X(k)) OR (T(2) AND Y(k))));
END GENERATE RegCntl;
tri_extern : trin PORT MAP (Data, Extern, BusWires );
reg0: regn PORT MAP (BusWires, Rin(0), Clock, R0);
reg1: regn PORT MAP (BusWires, Rin(1), Clock, R1);
reg2: regn PORT MAP (BusWires, Rin(2), Clock, R2);
reg3: regn PORT MAP (BusWires, Rin(3), Clock, R3);
tri0 : trin PORT MAP ( R0, Rout(0), BusWires );
tri1 : trin PORT MAP ( R1, Rout(1), BusWires );
tri2 : trin PORT MAP ( R2, Rout(2), BusWires );
tri3 : trin PORT MAP ( R3, Rout(3), BusWires );
regA : regn PORT MAP (BusWires, Ain, Clock, A );
alu :
WITH AddSub SELECT
Sum <= A + BusWires WHEN '0',
A - BusWires WHEN OTHERS;
regG : regn PORT MAP (Sum, Gin, Clock, G );
triG : trin PORT MAP (G, Gout, BusWires );
END Behaviour;
<<subccts.vhd>>
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package subccts is
COMPONENT REGN
generic(n:INTEGER:=8);
PORT( R:IN std_logic_vector(N-1 downto 0);
rin,clock:IN STD_LOGIC;
q: OUT STD_LOGIC_VECToR(N-1 downto 0));
end component;
component trin
generic(N:integer:=8);
port(X: IN STD_LOGIC_VECTOR(N-1 downto 0);
E: In STD_LOGIC;
F: OUT STD_LOGIC_VECToR (N-1 downto 0));
end component;
component dec2to4
port(w: In STD_LOGIC_vector (1 downto 0);
en:IN STD_LOGIC;
y :out std_logic_vector(0 to 3));
end component;
component upcount
port(clear,clock:IN STD_LOGIC;
Q:buffer std_logic_vector(1 downto 0));
end component;
end subccts;
<<dec2to4.vhd>>
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity dec2to4 is
Port (w : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
En : IN STD_LOGIC;
y : OUT STD_LOGIC_VECTOR(0 to 3));
end dec2to4;
architecture Behavioral of dec2to4 is
SIGNAL Enw : STD_LOGIC_VECTOR(2 DOWNTO 0);
begin
Enw <= En & w;
WITH Enw SELECT
y <= "1000" WHEN "100",
"0100" WHEN "101",
"0010" WHEN "110",
"0001" WHEN "111",
"0000" WHEN OTHERS;
end Behavioral;
<<regn.vhd>>
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity regn is
generic (n:integer:=8);
Port ( R : in std_logic_vector(N-1 downto 0);
Rin : in std_logic;
Clock : in std_logic;
Q : out std_logic_vector(N-1 downto 0));
end regn;
architecture Behavioral of regn is
begin
process
begin
wait until Clock'EVENT AND Clock = '1';
IF Rin = '1' Then
Q <= R;
end if;
end process;
end Behavioral;
<<trin.vhd>>
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity trin is
generic(n:integer:=8);
Port ( X : in std_logic_vector(N-1 downto 0);
E : in std_logic;
F : out std_logic_vector(N-1 downto 0));
end trin;
architecture Behavioral of trin is
begin
F <=(OTHERS => 'Z') WHEN E = '0' ELSE X;
end Behavioral;
<<upcount.vhd>>
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity upcount is
Port (clear,clock : IN STD_LOGIC;
Q : BUFFER STD_LOGIC_VECTOR(1 DOWNTO 0) );
end upcount;
architecture Behavioral of upcount is
begin
process(clock)
begin
IF (Clock'EVeNT AND Clock = '1') THEN
IF Clear = '1' THEN
Q <= "00";
ELSE
Q <= Q + '1';
END IF;
END IF;
END PROCESS;
end behavioral;
<<test_proc.vhd>>
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity test is
end test;
architecture behave of test is
component proc
PORT( Data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
Reset, w : IN STD_LOGIC;
Clock : IN STD_LOGIC;
F, Rx, Ry : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
Done : BUFFER STD_LOGIC;
BusWires : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0));
end component;
signal Data:std_logic_vector(7 downto 0);
signal Reset, w : std_logic;
signal Clock: std_logic := '0';
signal F, Rx, Ry : std_logic_vector(1 downto 0);
signal Done: std_logic;
signal BusWires: std_logic_vector(7 downto 0);
begin -- behave
Clock <= transport not Clock after 5 ns;
u1 : proc port map( Data,
Reset, w,
Clock,
F, Rx, Ry,
Done,
BusWires);
testbench: process
procedure command (
din : in std_logic_vector(7 downto 0);
cmd : in std_logic_vector(5 downto 0)) is
begin -- command
wait until Clock'event and Clock='1';
wait until Clock'event and Clock='0';
Data <= din;
F <= cmd(5 downto 4);
Rx <= cmd(3 downto 2);
Ry <= cmd(1 downto 0);
w <= '1';
wait until Clock'event and Clock='0';
w <= '0';
end command;
begin -- process testbench
Data <= "10101010";
Reset <= '1';
w <= '0';
F <= "00";
Rx <= "00";
Ry <= "00";
wait for 33 ns;
Reset <= '0';
command("00000000","000000"); --ld r0, 00
wait until Done='0';
command("00000001","000100"); --ld r1, 01
wait until Done='0';
command("00000010","001000"); --ld r2, 02
wait until Done='0';
command("00000011","001100"); --ld r3, 03
wait until Done='0';
command("00000100", "010100"); --mov r1, r0
wait until Done='0';
command("00000100", "100001"); --add r1, r0
wait until Done='0';
command("00000100", "100110"); --add r2, r1
wait until Done='0';
command("00000100", "101011"); --add r3, r2
wait until Done='0';
command("00000100", "101100"); --add r3, r0
wait until Done='0';
wait;
end process testbench;
end behave;
AND FINALLY THE MODEL SIM RUN
# Reading C:/Modeltech_5.7g/tcl/vsim/pref.tcl
# do test_proj.fdo
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 5.7g Compiler 2003.10 Oct 10 2003
# Model Technology ModelSim SE vcom 5.7g Compiler 2003.10 Oct 10 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling package subccts
# Model Technology ModelSim SE vcom 5.7g Compiler 2003.10 Oct 10 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity dec2to4
# Model Technology ModelSim SE vcom 5.7g Compiler 2003.10 Oct 10 2003
# -- Loading package standard
# -- Compiling architecture behavioral of dec2to4
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading entity dec2to4
# Model Technology ModelSim SE vcom 5.7g Compiler 2003.10 Oct 10 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity regn
# Model Technology ModelSim SE vcom 5.7g Compiler 2003.10 Oct 10 2003
# -- Loading package standard
# -- Compiling architecture behavioral of regn
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading entity regn
# Model Technology ModelSim SE vcom 5.7g Compiler 2003.10 Oct 10 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity trin
# Model Technology ModelSim SE vcom 5.7g Compiler 2003.10 Oct 10 2003
# -- Loading package standard
# -- Compiling architecture behavioral of trin
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading entity trin
# Model Technology ModelSim SE vcom 5.7g Compiler 2003.10 Oct 10 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity upcount
# Model Technology ModelSim SE vcom 5.7g Compiler 2003.10 Oct 10 2003
# -- Loading package standard
# -- Compiling architecture behavioral of upcount
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading entity upcount
# Model Technology ModelSim SE vcom 5.7g Compiler 2003.10 Oct 10 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_signed
# -- Compiling entity proc
# Model Technology ModelSim SE vcom 5.7g Compiler 2003.10 Oct 10 2003
# -- Loading package standard
# -- Compiling architecture behaviour of proc
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_signed
# -- Loading entity proc
# -- Loading package std_logic_unsigned
# -- Loading entity upcount
# -- Loading entity dec2to4
# -- Loading entity regn
# -- Loading entity trin
# Model Technology ModelSim SE vcom 5.7g Compiler 2003.10 Oct 10 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity test
# Model Technology ModelSim SE vcom 5.7g Compiler 2003.10 Oct 10 2003
# -- Loading package standard
# -- Compiling architecture behave of test
# -- Loading package std_logic_1164
# -- Loading entity test
# -- Loading package std_logic_arith
# -- Loading package std_logic_signed
# -- Loading entity proc
# vsim -L xilinxcorelib -lib work -t 1ps testbench
# Loading C:/Modeltech_5.7g/win32/../std.standard
# Loading C:/Modeltech_5.7g/win32/../ieee.std_logic_1164(body)
# Loading C:/Modeltech_5.7g/win32/../ieee.numeric_std(body)
# Loading C:/Modeltech_5.7g/win32/../ieee.std_logic_arith(body)
# Loading C:/Modeltech_5.7g/win32/../ieee.std_logic_unsigned(body)
# Loading work.testbench(behavior)
# ** Failure: Default binding had errors for entity "upcount" on the component declaration of line 38. See the compiler messages.
# Time: 0 ps Iteration: 0 Instance: /testbench File: upcnt_tb.vhd
# Fatal error at upcnt_tb.vhd line 45
# while elaborating region: /testbench
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./test_proj.fdo PAUSED at line 19
vlib work
vcom dec2to4.vhd regn.vhd upcount.vhd trin.vhd proc.vhd test.vhd
vsim test
add wave -r /*
run 400
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