I think it is a conventional style or rule of logic design, especially for ASIC design. Since, the final netlist to be passed to the backend for layout, had better to contains only two submodule, one is the core logic(RAM & PLL could be included as well), the other is the IOPAD or IOCELL , Power PAD. Core logic is to be place & Route at the center part of the die, and the IOPAD is placed around the core. So if there is any other cells, belongs to niether the core, nor the IOPAD, it's ambigious to place it.(inbetween the core block & IOPAD ring ?)....
Of couse, we know it should be placed in the core, so why not just put it included in the core logic.
Added after 15 minutes:
Sometimes that happens unintentionally. Ex, placing some ~(inverters), in front of some port signals of the submodules in the top modules. Synthesizer will create some inverter at the top of hierarchy.
Added after 6 minutes:
//BTW: Is 3-state buffer considered as glue logic?
//i.e.
//pci_devsel_n <= pci_devsel_n_o when pci_devsel_n_oe='1' else 'Z'
3-state buffer is allocated in the IO RING. But unlike FPGA, flip-flop is not included in the IOCELL in usual ASIC Cell library.