No glue logic in top level module?

[spriteice]

Hi guys,

I read somewhere that it is not advisable to use glue logic in top level module in FPGA design. It's alleged that only entity instantiation is allowed in the top-level module.

Could anyone point out the reason?

BTW: Is 3-state buffer considered as glue logic?
i.e.
pci_devsel_n <= pci_devsel_n_o when pci_devsel_n_oe='1' else 'Z'

 

[hamadeh]

Hi spriteice,

Glue logic means non-regular logic, normally a group of gates working asynchronous in static decisions. Regular logic like memory cells is not called "glue".
Glue logic consists of simple gates forming logical decisions. The gates can also be used as rs-ffs or dffs.

In other words, the term glue logic refers to the relatively small amount of simple logic that are used to connect ("glue") –and interface between- larger logic blocks, functions, or devices.)

This sort of logic is implemented in CPLDs, FPGAs or Gate Arrays.
In earlier times only about 1000 gates were called "glue logic". It is normally supporting higher integrated devices with additional functions (data transfer, buffering, reading sensors etc.)

 

[spriteice]

Thanks Hamadeh,

so is it true that glue logic should be avoided in the top-level entity of fpga design? If it is true, what is the reason?

 

[haosg]

it is only for convinience of budget submodule, timing or floorplan.
if your design is not big, dont care, because synthesis and auto place & route is flattern.

 

[zape]

If you implement glue logic in the top level module you may find that part of the design not optimized by the synthetiser. Anyhow, in your case, implementing the three-state buffer, I would recommend implementing it in the top, some synthesis tools like Leonardo do not work properly if you instantiate such IO in a lower level.

 

[ravelx]

I think it is a conventional style or rule of logic design, especially for ASIC design. Since, the final netlist to be passed to the backend for layout, had better to contains only two submodule, one is the core logic(RAM & PLL could be included as well), the other is the IOPAD or IOCELL , Power PAD. Core logic is to be place & Route at the center part of the die, and the IOPAD is placed around the core. So if there is any other cells, belongs to niether the core, nor the IOPAD, it's ambigious to place it.(inbetween the core block & IOPAD ring ?)....
Of couse, we know it should be placed in the core, so why not just put it included in the core logic.

Added after 15 minutes:

Sometimes that happens unintentionally. Ex, placing some ~(inverters), in front of some port signals of the submodules in the top modules. Synthesizer will create some inverter at the top of hierarchy.

Added after 6 minutes:



//BTW: Is 3-state buffer considered as glue logic?
//i.e.
//pci_devsel_n <= pci_devsel_n_o when pci_devsel_n_oe='1' else 'Z'

3-state buffer is allocated in the IO RING. But unlike FPGA, flip-flop is not included in the IOCELL in usual ASIC Cell library.

 

[Al Farouk]

my reply is from FPGA point of view, it is good practice to partion you design in modules so the sythesis, mapiing, floor planing and further updating would be easy, mainly in large design. you can not guide the placer to put the glue logic in certain position so it may cause trouble to the placer and router to put the modules in its optimum position. also, each time you make changes and rensynthesize, the glue get uncontroled place while you can fix the position of other modules.

 

[r_e_m_y]

Hi,

I think that the recommendation of providing only component mapping on a top architecture comes from re-use constraints.
If your design is correctly defined, all the functions are integrated in your different components. Your component may be reused "as it is" in an other design.
The only thing that should do a top module is to link all the component, and to map input and output. So High impedence interface is a part of the top level. InOut port are also part of top level, because it is recomended not to use InOut internal signals.

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