Nmos substrate connection

[petros85]

Hi all. I have runt into a DRC error :

MAXIMUM n+ DIFFUSION TO NEAREST p+ PICKUP SPACING(INSIDE P-WELL OR TWELL) IS 20um

I know this is resolved by adding taps or a guard ring around the device. Problem is that I get this error for one device that is quite big. So no matter how close I place the psub contacts I get the error marking the inside middle area of the device (that is further away than 20um from the taps.) There must be a way around this except resizing the nmos. (it is a diff pair in a one-line common centroid and I have tried to make it as square as possible)

Also I am using umc18nm process and I can't automatically create guard ring. It says guard ring template not set. So I manually placed psub contacts around the devices. In my smaller devices it worked nicely. Any advice on how to set the automatic guard ring creation?

 

[protonixs]

why not split that big transistors into smaller ones then make the arrangement ABAB?

Hi all. I have runt into a DRC error :

MAXIMUM n+ DIFFUSION TO NEAREST p+ PICKUP SPACING(INSIDE P-WELL OR TWELL) IS 20um

I know this is resolved by adding taps or a guard ring around the device. Problem is that I get this error for one device that is quite big. So no matter how close I place the psub contacts I get the error marking the inside middle area of the device (that is further away than 20um from the taps.) There must be a way around this except resizing the nmos. (it is a diff pair in a one-line common centroid and I have tried to make it as square as possible)

Also I am using umc18nm process and I can't automatically create guard ring. It says guard ring template not set. So I manually placed psub contacts around the devices. In my smaller devices it worked nicely. Any advice on how to set the automatic guard ring creation?

 

[petros85]

Yes that's a solution..I was trying to avoid it since I have already made a floorplan that will have to change now.

It seems too weird if you think about it it means that every device MUST have at least one dimension smaller than 20um. I thought that the 20um rule is from the edge of the diffusion area..not the WHOLE area.

 

[protonixs]

that is the only solution. violating this rule might trigger latch-up because of the potential difference between the 20um region, and beyond it.

Yes that's a solution..I was trying to avoid it since I have already made a floorplan that will have to change now.

It seems too weird if you think about it it means that every device MUST have at least one dimension smaller than 20um. I thought that the 20um rule is from the edge of the diffusion area..not the WHOLE area.