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diode connected PMOS parallel with diode connected NMOS

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Avien

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Hello Everyone!

in my circuit attached, i stacked diode connected NMOS parallel with stacked diode connected PMOS to generate voltage reference VH and VL.
Having in mind to help compensate their change during process variation. Am I correct with my assumption?
Can anybody help me in details of having this type of circuit?

Thanks!
 

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  • cur_volt.png
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Does your technology actually use floating substrates for all transistors?

Low side voltage references are typically used to bias NMOS transistors. Respectively they'll use the same type.
 

It looks kooky to me, if the PMOS meddles at all then
your current mirroring will be bent. -Maybe- there's a
model corner or settings that will give some desired
(non-1:1) transfer function at the far end of the bias
or maybe they really do want voltages and think that
"min(VTN, |VTP|)" offers a minimum-production-
variability (which it might) of a cheesy reference
voltage that values layout area and/or not-needing-
resistors-let-alone-precision over absolute accuracy).

I expect if you cared about tolerance you'd go with
a bandgap but a +/-10% "TTL threshold reference"
might well be made this way. Though I'd go with a
series NMOS+PMOS stack first off, most likely.

Since we don't know your care-abouts, suggest you
mock up a few alternatives and see what works best
at the far end of it all where specs probably define
a desired outcome.
 

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