macg84 said:Hallo and help me please...
...
net_psub net_subtap:Causes multiple stamped connection
net_psub net_subtap:has multiple stamped connection
I have connect one nmos bulk to ground, it is correct???
Bulk contacts for nfets on p-substrate (bulk), nwell contacts for pfets in nwell.macg84 said:Excuse me but the taps is the bulk contact in other words PD_C and ND_C?? or what else?
macg84 said:is it true?
macg84 said:Thanks for your very clear explanations...you are my hero
I think this is correct. However your Diva LVS log-file tells you there is a node /5 which most probably should be connected to VDD. Find it and connect it to VDD. I can't see it on your layout plot, so I suppose there is another n-well in your layout which isn't connected to VDD. Just find this node /5 .khaled2k said:I also receive an error no stamped connection for the PMOS even substrate is connected (or I think so).
I did the VDD connection using ND_C and NWELL and GND using PD_C. Is this correct?
Of course we feel this is a stupid error, but it actually could show up an essential problem. Unfortunately nobody cares to give an easily understandable explanation for what this error message means: it simply means there is a well which is not connected (by metal!) to any potential (for an n-well mostly, but not necessarily VDD, for a p-well - if it exists - mostly, but not necessarily VSS or GND) - this results in the "no stamped connection" error message, or a well or the substrate is connected via (more than one) taps to different potential levels - this creates the error message "multiply stamped connection".khaled2k said:I realy got bored from this design. It has been ages since the stupid error of "no stamped connection" chasing me.
erikl said:I think this is correct. However your Diva LVS log-file tells you there is a node /5 which most probably should be connected to VDD. Find it and connect it to VDD. I can't see it on your layout plot, so I suppose there is another n-well in your layout which isn't connected to VDD. Just find this node /5 .khaled2k said:I also receive an error no stamped connection for the PMOS even substrate is connected (or I think so).
I did the VDD connection using ND_C and NWELL and GND using PD_C. Is this correct?
Of course we feel this is a stupid error, but it actually could show up an essential problem. Unfortunately nobody cares to give an easily understandable explanation for what this error message means: it simply means there is a well which is not connected (by metal!) to any potential (for an n-well mostly, but not necessarily VDD, for a p-well - if it exists - mostly, but not necessarily VSS or GND) - this results in the "no stamped connection" error message, or a well or the substrate is connected via (more than one) taps to different potential levels - this creates the error message "multiply stamped connection".khaled2k said:I realy got bored from this design. It has been ages since the stupid error of "no stamped connection" chasing me.
Pls. see also my posting above from Wed, 28 Jan 2009 16:45 , which seems to have helped the OP macg84. Good luck!
Hi,AdvaRes said:Hi,
Correct the point that I mensonned in the figure and tell me what is the result.
khaled2k said:Hi,AdvaRes said:Hi,
Correct the point that I mensonned in the figure and tell me what is the result.
The two points (ND_C and PD_C) have the same x coordinates. They have the same distance to PMOS and NMOS respectively. I do not understand how to correct. Do you mean delete it or what?
Thanks in advance.
AdvaRes said:khaled2k said:Hi,AdvaRes said:Hi,
Correct the point that I mensonned in the figure and tell me what is the result.
The two points (ND_C and PD_C) have the same x coordinates. They have the same distance to PMOS and NMOS respectively. I do not understand how to correct. Do you mean delete it or what?
Thanks in advance.
Try one of the following modification
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?