Hi can anyone please clear my doubt. The network on Chip (NoC) is used only for the communication between the SoCs or it can be used for the communication between the different Processing elements in an SoC like adc, processor, tx-er etc., Thanks for any help
it is used for communication within a soc for different components like processor, memory, coprocessor, etc. Please look at the attachments in this thread: https://www.edaboard.com/threads/247860/#post1070052
I want to develop a low power NoC (regular and irregular) topology. i want to know how to write an NoC Topology coding in vhdl and how to simulate it in modelsim. can anyone please give me some examples for writing the vhdl code for NoC topologies.Thanks for any help
in the previous link i posted, it has an example of a noc design in vhdl from opencores. please look at it and start from there. then develop your own noc design by choosing what topology you want to have, router architecture, noc size etc. you need also to develop a network interface to act as an interface to the block that communicate through the noc. that's all i can help.
There is lots of literature available on architecture of a router, though u wont get any source code as such especially in VHDL. You start by chosing a topolgy (say grid or mesh) then you design a router for it. after that you start making your nodes based on these routers and interconnect them according to your topolgy. I designed one in verilog
There is lots of literature available on architecture of a router, though u wont get any source code as such especially in VHDL. You start by chosing a topolgy (say grid or mesh) then you design a router for it. after that you start making your nodes based on these routers and interconnect them according to your topolgy. I designed one in verilog