What will happen if you manually place in the schematic view two reverse diodes from VOC to gnd, the same as ?
Dear Suta,
I will try this soon in Lab, but what ar purposes of it and secondly where are the "avD41_4 and avD41_5 from the extracted view" you are referring to it
thanks
I am merciful today ;-)
In the schematic netlist you have only mosfets - model of channel below the gate oxide.
In the layout, your p-channel mosfets are putted in the n-wells, which are an island in the p-substrate. Every n-well forms p-n junction with substrate, modeled by nwd devices added by extractor into netlist.
In case, when your parameter x is zero, your pseudo resistor has the same 1.65V on terminals VA and VB. Transistors are biased with V_GS=0 - they are completely off.
I am pretty sure, that leakage of these guys is small. In schematic netlist, there is nothing connected between terminal VOC and gnd, so due to symmetry of structure V(VOC)=1.65 (average of VA and VB).
However, diodes has some leakage and thus finite resistance, so with completely off mosfets, these diodes pulling down terminal VOC to ground. Moreover, they are providing conditions to bias two mosfets into more cut-off region, changing ratio of resistances seen from VOC to gnd and to VA/VB, additionally decreasing potential at VOC.
The lesson for you.
Transistor is not only transistor but whole environment - modern nodes has complicated two or even three level hierarchical subcircuits, taking into account all junctions, contacts and necessary level of metalization. Old technologies like used by you 22 years old AMS C35, usually are not modeled on such deep level. And as you can see, ordinary diodes for n-well to p-substrate junction diodes are added after extraction, not before. Moreover, old models like used here bsim3.3 might has an issues in some extraordinary bias conditions - series connection of cut-off devices is such abnormal conditions (and even J. Baker mentioned about bsim3 issues in one of his book 20 years ago).
In real, for such conditions with VA=VB, you have transistors with no channels, only diodes, leakage current and potential accumulation region for some of them.
Basically, your VOC can be considered as "floating node" and can be on whatever potential.
These reverse connected diodes are in the extracted netlist. Just look there, I listed in my previous post the names under which they appear in the netlist.
Dear Suta,
Thank you for your continuous help,
I tried it but couldnt work
Such conclusion is too strong and is wrong in general. The devil is in details, as usual.Junus2012 said:Through your explanation, I now understand that this kind of resistor can not work with equal voltages at the terminals
This question is already answered.Junus2012 said:however, still one question in my mind which you forgot to answer me, what is the thing that made it work perfectly when I connect the bulk to the VDD rather than to the source.
Dear Suta,
Thank you for your reply, I ment I tried your suggestion but doesnt fix the problem
My suggestion was not meant to fix the problem, it was meant to show/explain the problem. You said you saw the problem in extracted netlist but not in schematic. So, I suggested to add those diodes in the schematic and see if you get the same or similar behavior as in the extracted simulation.
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?