...I've used ntiedown as substrate contact
I don't agree with this...ntiedowns are protection diodes NOT substrate contacts.
You must use subc for substrate contacts instantiation in schematic and layout instead!
I have no experience with calibre so if possible try with assura and give me the repsective error report.Also check this thread maybe has the answer to your problem :
https://www.edaboard.com/threads/219922/
What tech do you work on?
What tech do you work on?
At first forget tie-downs they are used for other purposes.
Ok,what type of transistors do you use? (regular fets or something else)
Each sub-cell (NAND,Inverter) must have it's own subc at it's schematic and some substrate contacts in it's layout.
The top level AND Gate must have it's own subc at the schematic and some substrate contacts in layout.
All these individual sub contacts of each cell are connected together with metal and finally connected to the VSS (GND or whatever) line of each cell.
Finally you end-up with metal the above sub contacts to the substrate contacts of the top-level and equally to the top level VSS line.
Do the above happen in your layout?
If yes,read the document that i and oermens suggest in the thread https://www.edaboard.com/threads/219922/ and make use of SXCUT.
In my opinion,only in this way you will solve your issue in parallel with IBM's recommendations.
Good luck
At first forget tie-downs they are used for other purposes.
Ok,what type of transistors do you use? (regular fets or something else)
Each sub-cell (NAND,Inverter) must have it's own subc at it's schematic and some substrate contacts in it's layout.
The top level AND Gate must have it's own subc at the schematic and some substrate contacts in layout.
All these individual sub contacts of each cell are connected together with metal and finally connected to the VSS (GND or whatever) line of each cell.
Finally you end-up with metal the above sub contacts to the substrate contacts of the top-level and equally to the top level VSS line.
Do the above happen in your layout?
If yes,read the document that i and oermens suggest in the thread https://www.edaboard.com/threads/219922/ and make use of SXCUT.
In my opinion,only in this way you will solve your issue in parallel with IBM's recommendations.
Good luck
SXCUT:drawing is not used to solve LVS problems but to generate isolated substrate regions, using it for anything else will prevent detection of soft-connect violations
I didn't say that SXCUT is used to solve LVS issues.It would be at least foolish the existence of a a layer that solves LVS errors (or cheats LVS deck if you want in other words) without having an actual or reasonable purpose in layout.
My intention is to guide nana_7488 to properly use the things that IBM recommends in their documents for proper substrate declaration in layout.
That's all.
Could you please explain the term "soft-connection"?
As fas as i can understand a connection can exist (right or wrong is another matter) or not exist.
In your first image I do not see any BP implant, this means you have no substrate contacts in the layout so (assuming this is what you meant to have in the schematic) you just need to stamp the substrate, which you named sub! in the schematic
To name the substrate terminal add a label or pin with the text in SXCUT:label
This layout does not seem to correspond to the initial netlist please post the new netlists if you still have problems
---------- Post added at 10:04 ---------- Previous post was at 10:01 ----------
Hi dgnani
I have put the subc in the layout for each cell.What do you mean by stamping the substrate and name it?Do I have to name it on layout for inv and nand, or just name it in top layout?
and where should i put the label, is it at the subc? Sorry because I'm too confused between your suggestion and jimito13.
I have try to put global subc in top level schematic, still didn't work, and this layout without the global subc.
please check my layout. Based on your opinion, I can't put SXCUT layer, so do I need it or not?When I tried to put the layer as JImito13 said, other error regarding to subc gone, but as you said, there are soft substrate pin error.
Thanks
Your problem is very simple but you keep changing things around and not post all relevant data so...
- pick one configuration
- post the schematic plots of all 3 schematics (top inv and nand)
- post the top-layout
- post both calibre netlists
then we can discuss the solution
please add a "sub!" label to your layout using layer "SXCUT:label" and place it anywhere (outside any device) in your layout...
... and let us know if it works
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