negative timing check

[useless_skew]

Can anybody explain me about negative timing checks?

 

[chipmonkey]

If you are using VCS for simulation, by default this is not enabled. Use the option +neg_tchk during compilation to enable it.

 

[jpvSoccer]

Hi, are you talking about negative hold timing check values?

If so, they are possible and just mean that the data can change before the clock and still be sampled properly.

 

[chipmonkey]

@jpvSoccer: you are correct.

The option mentioned is to enable this check on VCS. else VCS will replace these values with 0.

PS: please ignore my comment on negedge check

 

[jpvSoccer]

Hi,

The default operation of some simulators is to ignore negative timing checks during back-annotation.

This approach is more conservative than automatically allowing negative timing checks; a hold of 0 is more conservative than a hold of -50ps.

As such, if you want a more conservative hold check, stay with the simulator default operation.

If holds are killing you and you know you have margin in the form of negative hold values, tell your simulator to allow them.