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negative HOLD values in SDF file

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sisari

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Nobody more experienced in logic synthesis can help me with this ??
What does negative HOLD timing check in SDF file means ? Need help!
Plz PM me!
 

Nobody

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it have been asked many times . look in your sold solve it articles with keyword search.
 

synq

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negative holdtime check in sdf

From my little ignorance..You can't say negative holdtime is a insuffecient parameter but it still have good use like allowing to change the state for a further instance even after a clock edge..like so..but the fact the verilog compilers in especially big guns still have a confusing picture about the convergence of edges..
The link below is the best thing I can offer to see what it actually holds the story.

http://www.deepchip.com/items/0382-08.html

cheers mate...
 

tom123

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negative hold time means that the signal can change before clock edge.

best regards


sisari said:
Nobody more experienced in logic synthesis can help me with this ??
What does negative HOLD timing check in SDF file means ? Need help!
Plz PM me!
 

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