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is 6ns as min or max delay?fpga intentionally adds an internal delay of 6 ns to the data input
What's the required clock frequency?specify the setup time as 11 ns
in my understanding, defining the -1ns as a hold time on the input port will just force the tool to implement an internal to the synthesized block combo logic with min delay of 1ns on this path.specify ... hold time as -1 ns
In this case, what's the min/max delays will be on the data path from the input port to the register?You can now specify the setup time as 11 ns and the hold time as -1 ns.
I still don't understand this...Let's say a register has a setup time requirement of 5 ns, and a hold time requirement of 5 ns. Now, suppose the fpga intentionally adds an internal delay of 6 ns to the data input. You can now specify the setup time as 11 ns and the hold time as -1 ns.
Is 6 ns in min or max delays?suppose the fpga intentionally adds an internal delay of 6 ns to the data input
I'm asking about timing constraints on the input/output ports of the design. What them are?setup time is a minimum of 11 ns. The hold time is a minimum of -1 ns
I just TOLD you: 11 ns/-1ns.I'm asking about timing constraints on the input/output ports of the design. What them are?
Waw! it's something new in the Digital Design! Clock period is irrelevant for the Setup time constraint - good stuff!Irrelevant!!!! Setup and hold times relate only to a clock edge. The period has ABSOLUTELY NOTHING TO DO WITH IT.