Negative Hold on Input and Output Delays - is there a sense?

[ivlsi]

Hi All,

Is there a sense to define Negative Hold on Input and Output Delays (synthesis timing constraints)?

How does it exactly work?

Thank you!

 

[barry]

This is sort of a 'trick' fpga vendors use. Let's say a register has a setup time requirement of 5 ns, and a hold time requirement of 5 ns. Now, suppose the fpga intentionally adds an internal delay of 6 ns to the data input. You can now specify the setup time as 11 ns and the hold time as -1 ns.

 

[ivlsi]

fpga intentionally adds an internal delay of 6 ns to the data input

is 6ns as min or max delay?

specify the setup time as 11 ns

What's the required clock frequency?

specify ... hold time as -1 ns

in my understanding, defining the -1ns as a hold time on the input port will just force the tool to implement an internal to the synthesized block combo logic with min delay of 1ns on this path.

You can now specify the setup time as 11 ns and the hold time as -1 ns.

In this case, what's the min/max delays will be on the data path from the input port to the register?

 

[barry]

Setup and hold have nothing to with 'required' frequency (other than limiting period to setup+hold). The -1ns hold just means that your data signal has to be valid only up to 1ns before the clock edge.

 

[ivlsi]

barry, it seems we are talking about totally different tools... Actually I'm not a FPGA designer and have experience only with ASIC tools...
The definitions, which you are talking about, are completely different in the ASIC world.
Anyway, thank you for your comments.

 

[matter]

Hi ivlsi,
I think that barry hit the nail on the head with his example for your question. Just forget about fpga in his example and go through it again. It answers your question clearly.

To be more explicit, "YES" it does make sense to have -ve values in i/o delay constraints. We deal with it all the time in asic world. I have seen it in several asic chip designs. It is perfectly OK to have -ve values for setup/hold/input delay/output delay....

Best Regards

 

[ivlsi]

Let's say a register has a setup time requirement of 5 ns, and a hold time requirement of 5 ns. Now, suppose the fpga intentionally adds an internal delay of 6 ns to the data input. You can now specify the setup time as 11 ns and the hold time as -1 ns.

I still don't understand this...

Let's talk in terms of input delays. What input min/max delays should be set on this input port in order to fulfill the described above timing ? What internal logic would be generated (in terms of min/max delays) as a result of these constraints?

Thank you!

 

[barry]

Simply said, the setup time is a minimum of 11 ns. The hold time is a minimum of -1 ns.

Maybe you should try drawing a timing diagram.

 

[ivlsi]

suppose the fpga intentionally adds an internal delay of 6 ns to the data input

Is 6 ns in min or max delays?

setup time is a minimum of 11 ns. The hold time is a minimum of -1 ns

I'm asking about timing constraints on the input/output ports of the design. What them are?

 

[barry]

I'm asking about timing constraints on the input/output ports of the design. What them are?

I just TOLD you: 11 ns/-1ns.

 

[ivlsi]

input max delay of 11ns and input min delay of -1ns? What's the clock period?

 

[barry]

Irrelevant!!!!

Setup and hold times relate only to a clock edge. The period has ABSOLUTELY NOTHING TO DO WITH IT.

 

[ivlsi]

Irrelevant!!!! Setup and hold times relate only to a clock edge. The period has ABSOLUTELY NOTHING TO DO WITH IT.

Waw! it's something new in the Digital Design! Clock period is irrelevant for the Setup time constraint - good stuff!

- - - Updated - - -

Take a look at this post: https://www.edaboard.com/threads/269890/
Are the constraints correct there?

 

[barry]

If you believe that clock period has ANYTHING to do with the setup constraint, you need to go back and educate yourself about what setup and hold really mean.