This is sort of a 'trick' fpga vendors use. Let's say a register has a setup time requirement of 5 ns, and a hold time requirement of 5 ns. Now, suppose the fpga intentionally adds an internal delay of 6 ns to the data input. You can now specify the setup time as 11 ns and the hold time as -1 ns.
in my understanding, defining the -1ns as a hold time on the input port will just force the tool to implement an internal to the synthesized block combo logic with min delay of 1ns on this path.
You can now specify the setup time as 11 ns and the hold time as -1 ns.
Setup and hold have nothing to with 'required' frequency (other than limiting period to setup+hold). The -1ns hold just means that your data signal has to be valid only up to 1ns before the clock edge.
barry, it seems we are talking about totally different tools... Actually I'm not a FPGA designer and have experience only with ASIC tools...
The definitions, which you are talking about, are completely different in the ASIC world.
Anyway, thank you for your comments.
Hi ivlsi,
I think that barry hit the nail on the head with his example for your question. Just forget about fpga in his example and go through it again. It answers your question clearly.
To be more explicit, "YES" it does make sense to have -ve values in i/o delay constraints. We deal with it all the time in asic world. I have seen it in several asic chip designs. It is perfectly OK to have -ve values for setup/hold/input delay/output delay....
Let's say a register has a setup time requirement of 5 ns, and a hold time requirement of 5 ns. Now, suppose the fpga intentionally adds an internal delay of 6 ns to the data input. You can now specify the setup time as 11 ns and the hold time as -1 ns.
Let's talk in terms of input delays. What input min/max delays should be set on this input port in order to fulfill the described above timing ? What internal logic would be generated (in terms of min/max delays) as a result of these constraints?
If you believe that clock period has ANYTHING to do with the setup constraint, you need to go back and educate yourself about what setup and hold really mean.