Mmmm... That is a tough one.
Here is what I will do. I am assuming your LVDS does not run that fast and you have series
and parallel termination. I will play with the termination to get close to the LVDS level. But
watch out for signal integrity issue. I will use either Hyperlynx or Cadence for simulation.
If your LVDS do tri-state, then you may put a cap in parallel to slow the rising and falling
edge so between bits will be closed to 2.5V. But that will mean different level depending
on your bit rate.
There is no way inside the FPGA that you can do to give you a 2.5V output.