Need urgent help for Xilinx FPGA!!!

[EDA_hg81]

By accident, we have connected the Vcco for LVDS output signals from 2.5V to 3.3V on PCB.

We still can assign the signals to LVDS level inside program, but the I/O voltage at outside is 3.3V.

What we should do to correct this?

We do not have time to fix PCB.

Any suggestions are appreciated.

 

[Gunship]

By accident, we have connected the Vcco for LVDS output signals from 2.5V to 3.3V on PCB.

We still can assign the signals to LVDS level inside program, but the I/O voltage at outside is 3.3V.

What we should do to correct this?

We do not have time to fix PCB.

Any suggestions are appreciated.

Mmmm... That is a tough one.
Here is what I will do. I am assuming your LVDS does not run that fast and you have series
and parallel termination. I will play with the termination to get close to the LVDS level. But
watch out for signal integrity issue. I will use either Hyperlynx or Cadence for simulation.
If your LVDS do tri-state, then you may put a cap in parallel to slow the rising and falling
edge so between bits will be closed to 2.5V. But that will mean different level depending
on your bit rate.

There is no way inside the FPGA that you can do to give you a 2.5V output.

The last resort is to fix the PCB.

Good luck,

Gunship