Need to know the Inputs at each stage in Physical Design? Please respond...

[SravanPD]

Kindly give me an outline about inputs in each stage i,e: Simulation, Floor Planning, Placement, CTS, Routing. of PD

 

[arun@vlsi]

Inputs for Physical Design

.lef (Layout Exchange Format) --> physical library
.lib (liberty format) --> logical/timing library (both slow and fast library)
.io (Input/output) --> I/O pad libraries
.sdc (Synopsys Design Constraints) --> constraint file which is obtained from synthesis output
.v or .vhd (Verlog or VHDL code) --> RTL code of the design

 

[arun@vlsi]

-->for simulation only need is the RTL code (.v/.vhd) and for verification, corresponding test-bench is needed.

-->for synthesis the inputs are
1) .v/.vhd (verilog/ VHDL code) - technology independent
2) design constraints
3) .lib (timing library)
outputs of synthesis
1).vg (Verilog gate level netlist) - technology dependent
2).sdc (Synopsys design constraints)