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VLSI PD- discussion

VLSI PD- discussion

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Hi....i want to know how can i reduce the count of buffers and inverters introduced during the placeOPt clockOPt or routeOpt stages...

devaVLSI

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Hi....i want to know how can i reduce the count of buffers and inverters introduced during the placeOPt clockOPt or routeOpt stages...
 

riti

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1. give path groups as optimization through path groups ahs been done at placeopt, clockopt and routeopt stages.
2. If hold violations are more at clockopt stage, tool will insert more hold buffers at route opt stage.
3. try to bound the logic at place opt for reducing buffers/inverters. place macros near to ports they are talking, place RP toghter.
 

devaVLSI

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1. give path groups as optimization through path groups ahs been done at placeopt, clockopt and routeopt stages.
2. If hold violations are more at clockopt stage, tool will insert more hold buffers at route opt stage.
3. try to bound the logic at place opt for reducing buffers/inverters. place macros near to ports they are talking, place RP toghter.

Thanks,

What is the RP here?
And what things to look into for creating path groups?
 

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