need test bench urgent!!!

[Venkat Esh]

1 --------------------------------------------------
2 ENTITY counter IS
3 PORT (clk: IN BIT;
4 count1, count2: OUT INTEGER RANGE 0 TO 9;
5 END ENTITY;
6 --------------------------------------------------
7 ARCHITECTURE dual_counter OF counter IS
8 SIGNAL temp1: INTEGER RANGE 0 TO 10;
9 BEGIN
10 -----counter 1: with signal:-----
11 with_sig: PROCESS(clk)
12 BEGIN
13 IF (clk'EVENT AND clk='1') THEN
14 temp1 <= temp1 + 1;
15 IF (temp1=10) THEN
16 temp1 <= 0;
17 END IF;
18 END IF;
19 count1 <= temp1;
20 END PROCESS with_sig;
21 -----counter 2: with variable:-----
22 with_var: PROCESS(clk)
23 VARIABLE temp2: INTEGER RANGE 0 TO 10;
24 BEGIN
25 IF (clk'EVENT AND clk='1') THEN
26 temp2 := temp2 + 1;
27 IF (temp2=10) THEN
28 temp2 := 0;
Figure 7.2
Simulation results from the counters of example 7.3.
184 Chapter 7
29 END IF;
30 END IF;
31 count2 <= temp2;
32 END PROCESS with_var;
33 END ARCHITECTURE;
34 --------------------------------------------------

 

[rca]

no question, no problem?
do you beleived we will do your homework, student?

 

[alexan_e]

You didn't even bother to select the proper code part, you just copy/pasted everything, even the image description

Figure 7.2
Simulation results from the counters of example 7.3.
184 Chapter 7