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timing closure is when you modify your design to meet timing specs... you give constraints to the tool and it makes modifications to your design based on those constraints...to have a design that meets its specified performance
so you can say that you have a "timing closure" when your timing specs are satisfied
so you need to watch out for timing in different processes such as logical synthesis, clock tree synthesis, place and route...
go through questions asked in this forum on STA and tool related timing issues.Come out with some particular issues on timing we will have discussion on that.
hi,
Timing closure is itself is a vast ocean. I guess u r a student, please go through " timing verification of ASICs " by Farzad Nekoogar.I Will definitely be able to help you out if you have some specific issues.
Do put some effort to go through this forum, u ll get plenty of materials.
With due respect,dear userz, please go through this forum before posting any queries, instead of vaguely posting a query,that IMHO reflects the amount of interest and dedication to gain and more importantly share knowledge.
timing closure is to meet your timing constrain,so you will fix many setup and hold timing violation. It's very important for us to watch it carefully!
But Fixing Setup/Hold Needs familiarity about those critiacl paths.Right??
While Facing timing issues,Its hard to find the soln for less Experienced people.
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