Need some Help for VERILOG code

[Adnan86]

Hi
I write below code for define 4 type of address, the code work correctly. but I want something more to add.
I want to Reset signal (func), anytime that (func) change. In this code if I change func, (addr) will be change until reach 100. But I want to reset (addr), anytime (func) change.
thanks for consideration and giving your time.

always @ (posedge clk) begin
	if (rst)
		addr <= 0;
	else if (addr < 100)
		addr <= addr + 1;
	else
		addr <= 0;
end

// -- define wave
always @ (posedge clk ) begin
	case (func)
		2'b00 : begin			// sin wave
					addra <= addr + 0;
				  end
		2'b01 : begin			// square wave
					addra <= addr + 100;
				  end
		2'b10 : begin			// triangler wave
					addra <= addr + 200;
				  end
		2'b11 : begin			// sawtooth wave
					addra <= addr + 300;
				  end
		default : addra <= 0;
	endcase

 

[TrickyDicky]

how about this:

func_r <= func;

if (rst || ( func != func_r)) then
  addr <= 0;