Need resources on sti stress - bulk connection/substrate tap

[vandenm]

sti layout cmos

Hi

Does anyone have any documentation or web links on sti stress? I'm particularly interested in where to position bulk connection/substrate taps. Everything I have read so far does not cover this area.

On larger processes I have layed out devices with say an M=6 in the following way:

b s g d g s b s g d g s b s g d g s b

I appreciate that critically matched devices should have dummy poly or individually placed transistors with or without dummy poly to relieve sti.

My question is, should bulk connections be avoided next to the source pins and should they be placed top or bottom or a ring if space permits?

Your help would be much appreciated.

Cheers

 

[scottieman]

silicon sti stress

Hi

Does anyone have any documentation or web links on sti stress? I'm particularly interested in where to position bulk connection/substrate taps. Everything I have read so far does not cover this area.

On larger processes I have layed out devices with say an M=6 in the following way:

b s g d g s b s g d g s b s g d g s b

I appreciate that critically matched devices should have dummy poly or individually placed transistors with or without dummy poly to relieve sti.

My question is, should bulk connections be avoided next to the source pins and should they be placed top or bottom or a ring if space permits?

Your help would be much appreciated.

Cheers

Sorry that I cannot get your question.
Do you mean how the stress due to STI affect the matching of transistor?

If yes, can you tell me how the two transistors are layouted?

Thanks
Scottie

 

[vandenm]

cmos sti

Hi

Managed to add a picture!

>>Do you mean how the stress due to STI affect the matching of transistor?

Yes I do, but also with respect to possitioning of subtrate taps. The source and subtrate are normally connected (connection not shown) but the active is not joined between the substrate tap and pmos as the designers want the flexibility of disconnecting source from the substrate.

Cheers

 

[scottieman]

Re: cmos 0.18 sti stress

Hi

Managed to add a picture!

>>Do you mean how the stress due to STI affect the matching of transistor?

Yes I do, but also with respect to possitioning of subtrate taps. The source and subtrate are normally connected (connection not shown) but the active is not joined between the substrate tap and pmos as the designers want the flexibility of disconnecting source from the substrate.

Cheers

According to the visual you presented here, and let me make a "BIG" assumption:

The active region for substrate contact between transistors is large enough to buffer all the stress due to STI

Then, all transistor should be the same

That is my understanding and hope it helps
Scottie

 

[rfsystem]

Re: cmos 0.18 sti stress

To my understanding STI creates mechnical stress. So simple avoid placing gate areas near the nwell/pwell borders. The lateral mechanical stress change the threshold voltage depending on orientation but I do not know the amount of the effect.