need PLL scheme or special solution to fit the requirements

[mqblue]

PLL solution help

Hi guys,

I am seeking a PLL scheme that works at about 2.5GHz and can lock the frequency as well as the phase within 1 us. I think maybe many PLLs can do this. but the special thing is that the current system use an universal 48MHz crystal and we can not apply the frequency changes directly on this crystal. Maybe we can only change division factor N to achieve this adjustment.

And here is the problem, actually in our system, we do not need PLL that with a big turnable range, we have known the frequency offset will be within 100 ppm. However, what is critical is we require the PLL could achieve the high resolution, which maybe within 1 ppm. I read some literature about fractional-N pll but find it really slow compared with the requirement of our system, if we use many bits of input words to get finer resolution.

So, in sum, we need a "PLL" that have a high resolution (within 1 ppm), fast locking time (within 1 us) and with the reference clock of 48 MHz from a universal crystal. The only good thing is that we know the frequency offset is always within a very small range, so we did not need a very large tunable range for this PLL. Therefore, with regard to this kind of requirement. What kind of PLL scheme or special solution shall I take ?

Thank you all in advance. Very appreciate for any of your help.

Qian[/b]

 

[mengcy]

PLL solution help

Hi,I don't know what do you mean by high resolution.which is usually defined by the hopping frequency around the center frequency.For example,in bluetooth system the local oscillator could lock at 2.4G~2.525G with 1M resolution.

1ppm resolution means that your hopping frequency is 2.5k.

Fractional-N is needed here.Because 1us locking time is very short so the bandwidth should be set at several Mrad.That would cause a very large in-band noise.

 

[mqblue]

Re: PLL solution help

Hi,I don't know what do you mean by high resolution.which is usually defined by the hopping frequency around the center frequency.For example,in bluetooth system the local oscillator could lock at 2.4G~2.525G with 1M resolution.

1ppm resolution means that your hopping frequency is 2.5k.

Fractional-N is needed here.Because 1us locking time is very short so the bandwidth should be set at several Mrad.That would cause a very large in-band noise.

Hi, Thanks for your reply. Sorry for the confusion. I think I should say more about our system. Actually, I am trying to implmenet the timing recovery process. Now we have achieved the simulation of M&M timing recovery feedback loop and wish to go further to explore how to apply this timing error signal on our ADC. About the frequency resolution I mentioned, because the final performance of the timing recoevery should make the frequency offset within 1 ppm, so the sensitivity of our frequency adjustment should also be finer than 1ppm, right?. But when we want to apply this feedback loop on ADC, we found the clock provided for ADC is generated by a ingerger-N PLL with a 48MHz universal crystal. So things comes a little complicated because it is very difficult to achieve such a fine frequency by using a fractional-N PLL. because I think maybe the preciseness of 1 ppm may require a divider like 55.1032, which need a very long sequence of 55/56 to generate. And for a 48MHz reference frequency, it means the huge delay compared with the 1us converge time we required.

So, maybe we should not apply franctional_N pll in the timing recovery feedback system? I just want to know if I understand this kind of pll wrongly or is there any thing we can do to fit this situation.

Thank you. Sorry that my english expression of such a technical thing is quite difficult to understand. I appreciate for your patient and I would like to explain much more, if you still willing to help me.

Qian