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Need paper on open loop duty cycle correction block

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mbalakri

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Duty cycle correction

Hi,

Do anyone have any paper regarding open loop duty cycle correction block. I read a paper which talks about delaying the clock input and then having an interpolator to get 50% duty cycle. (Paper - Open-loop full-digital duty cycle correction circuit - C. Yoo, C. Jeong and J. Kih)

Any more info will help to understand and also some information regarding interpolator. Am not sure about what type of interpolator to be used.
 

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