Ashish Agrawal
Member level 3
I am using system verilog to code a state-machine.
I defined the state variables using enum types...
typedef enum logic [1:0] {A, B, C} state_t;
state_t curr_state, next_state;
I am using the "unique case" statement for coding the combo block
always_comb
begin
unique case (curr_state)
A: ---------
B: ---------
C: ---------
endcase
end
Do I need to specify "default" statement? How simulation and synthesis tool behaves by using/not using "default" in this scenario?
How tool (synthesis/simulation) behaves differently with the following combinations with respect to "default" statement
1) enum types and unique case
2) Constant parameter declarations and unique case
3) enum types and case (without unique)
4) constant parameter declarations and case (without unique)
Thanks,
Ashish
I defined the state variables using enum types...
typedef enum logic [1:0] {A, B, C} state_t;
state_t curr_state, next_state;
I am using the "unique case" statement for coding the combo block
always_comb
begin
unique case (curr_state)
A: ---------
B: ---------
C: ---------
endcase
end
Do I need to specify "default" statement? How simulation and synthesis tool behaves by using/not using "default" in this scenario?
How tool (synthesis/simulation) behaves differently with the following combinations with respect to "default" statement
1) enum types and unique case
2) Constant parameter declarations and unique case
3) enum types and case (without unique)
4) constant parameter declarations and case (without unique)
Thanks,
Ashish