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Need Low-Jitter Clock Multiplier

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EDA_hg81

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Do any one knows any Low-Jitter Clock Multipliers ?

The requirements for this Clock Multiplier is as follow:

The Max output is 300 MHZ.

The input clock has to be multiplied by 3.5.

Thanks.
 

I don't know if there any standalone clock multipliers available but a PLL can do that for you.

**broken link removed**
 

    EDA_hg81

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Thank you very much.

let me to check this site.
 

can you give more details what are planning to run at that speed??? Might be internal PLL in FPGA will work?? or perhaps DDR
 

    EDA_hg81

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What I want to do is to realize a parallel to serial LVDS bus.

Hope this is enough for you.
 

OK why don't use internal PLL in FPGA?? because if you have clock running separate from data y how do you planning to meet hold and set up time?
 

    EDA_hg81

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LVDS is Low Voltage Differential Signalling. Its basically a serial transmission that uses differential outputs/inputs, like USB (D+ D-). To achieve LVDS in FPGA's, there are a couple of points to be considered..


1. Does the FPGA I/O support LVDS.
2. If so, what is the maximum LVDS speeds attainable.
3. Pin and PAD placement for LVDS signals to avoid Signal integrity problems.
4. Necessary clocks are present for generating the LVDS data and clock.


In order to generate LVDS data (Tx), the data will have to be sent using DDR, ie, on both the clock edges. Thus, to implement a LVDS Tx, we need to first pass the data thro' a DDIO (Double-data rate IO) function to get the DDR data. This data is then transmitted serially using the DDR clock that is also generated internally.

For LVDS calculations, if we need to transmit data at 300Mbps, then the clock has to be of 150MHz (DDR clock). You can use the PLLs that are present in the FPGA to generate this clock and then pass it through the DDR function.

LVDS signals have a pair of differential data signals, a differential clock and then the single-ended Acknowledge and Block Complete signals.

For example, in the ADSP processors the Link Ports are LVDS signals. They are 4-bit LVDS that can be configured as 1-bit LVDS too, ie,

LVDS clock+
LVDS clock-
LVDS data0+
LVDS data0-
LVDS data1+
LVDS data1-
LVDS data2+
LVDS data2-
LVDS data3+
LVDS data3-
Acknowledge
Block Complete

If you want to send LVDS data at 300Mbps, the LVDS clocks will be 150MHz each. This when the data is sampled and transmitted at both edges will lead to a data rate of 300Mbps.

In your case, the clock is at 300MHz, so the data rate you are trying for is 600Mbps. First check out if the FPGA I/O pins support 600Mbps LVDS data rate. If so, use the LVDS functions that are available in the tool or use the DDR functions and PLLs to generate the clocks.[/b]
 

    EDA_hg81

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Thank you very much for your suggestions.

I am going to try.
 

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