Need help with this code

Status
Not open for further replies.

haneet

Full Member level 3
Joined
Nov 7, 2006
Messages
160
Helped
14
Reputation
28
Reaction score
1
Trophy points
1,298
Activity points
2,219
Hi,
I'm trying a small piece of code and i'm not sure why my results are "x". Infact, the assigned value b in this code is also "x".


Code Verilog - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
module test;
 
wire a,b,c;
 
assign b=1'b1;
c=b;
 
initial begin
$display("output value c=%b b=%b",c,b);
end
assign #20 b=1'b0;
initial begin
$display("output value c=%b b=%b",c,b);
end
 
endmodule



Thanks in advance
 
Last edited by a moderator:

Yeah you can't assign it in two places at once, that is the same as shorting two wires on a board with a logic 1 and logic 0, the end result is the stronger driver wins. In simulation this results in an X for I'm unsure whether it is a 1 or 0.
 
Reactions: haneet

    haneet

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.
Cookies are required to use this site. You must accept them to continue using the site. Learn more…