Need Help with opening a file and reading it only once

[kassie]

I am trying to write some code to read in a text file where I have my input stored. I am able to read it in; but I don't know how to read it only one time. After I read the first line from the file I convert the input from integer to std_logic_vector. After I read in the data I need to shift it out one bit at a time. The comments in my code should be clear enough to give an idea of how I want to shift the data out. Originally I used signals. However my compilier gave me errors so I changed to variables and it worked. I may have issues with conflicting libraries. Now that my errors are gone it doesn't appear as though I'm shifting out data. When I tried to shift out the least significant bit from the LSByte first; my variable that I pass it to doesn't change. The rate I'd like to shift out the data is at the baud rate. I have 20 bits of data that I'd like to shift one bit per clock cycle. Therefore I have used a counter. My input are decimal numbers up to 1026. I am writing this for a testbench. The testbench is supposed to input stimuls for downloading a file via serial communication link RS-422.

Code is attached

 

[nand_gates]

Where is the code???

 

[abdulahad100]

there is no code attached and im unable to understand ur problem. maybe viewing the code will give me any hints. attach it with ur post.

 

[kassie]

I tried to attach the file, but I guess it didn't work becuase it was the wrong extension. Let me try to attach it again and paste it just in case.


signal ClkBR : std_logic;
signal Counter_BR : INTEGER;

Baud_rate: process
begin
ClkBR <= '0'; -- 19200 bits per second
wait for 52 us;
ClkBR <= '1';
wait for 52 us;
end process;
--------------------------------------
-- Generate 1MHz clock (1uS)
--------------------------------------

Counter_BR_process (ResetNotIn, ClkBR)
begin
if ResetNotIn='0' then
Counter_BR <= 0;
elsif rising_edge(ClkBR) then
if Counter_BR < 20 then
Counter_BR <= Counter_BR + 1;
else
Counter_BR <= 0 ;
end if;
end if;
end process;

read_input: process (ClkBR)

FILE file_in : text;
VARIABLE line_in : INTEGER;
VARIABLE buff: line;
variable line_in_vec: std_logic_vector(15 downto 0);
variable Dout_LSByte: std_logic_vector(9 downto 0);
variable Dout_MSByte: std_logic_vector(9 downto 0);
variable SDout: std_logic;


-- function conv_std_logic_vector(line_in: 16 return std_logic_vector;

begin
file_open(file_in, "prf_data.txt", READ_MODE);
if rising_edge(ClkBR) then
if Counter_BR = 0 then
-- Read lines until you get an EOF then break out and close file
readline(file_in, buff); -- file
READ(buff, line_in); -- read integer from file
line_in_vec := conv_std_logic_vector(line_in, 16);
Dout_LSByte := STOPBIT & line_in_vec(7 downto 0) & STARTBIT;
Dout_MSByte := STOPBIT & line_in_vec(15 downto 8) & STARTBIT;
elsif Counter_BR > 0 and Counter_BR < 20 then
-- shift register for 20 bits of serial data (shift one bit at a time)
SDout := Dout_LSByte(0); -- shift LSB of LSByte first
Dout_LSByte(8 downto 0) := Dout_LSByte(9 downto 1); -- shift LSByte next
Dout_LSByte(9) := Dout_MSByte(0); -- shift LSB of MSByte next
Dout_MSByte(8 downto 0) := Dout_MSByte(9 downto 1); -- shift MSByte last
end if;
end if;
file_close(file_in);
end process;

 

[mexico_mike]

If you only want to do something once, just create a boolean variable and set
it's default to 'false'. Check the variable before you do your read. Then do your read or whatever, and then set the variable to true.

VHDL i.e.
...
read: process(clk,reset)
variable did_it: boolean := false;
begin
if reset = '1' then
-- blah blah blah;
did_it := false;
elsif rising_edge(clk) then
if not did_it then
-- do the read
did_it := true;
else
-- skip the read;
end if;
end if;
end process read;

hope this helps
Mike

 

[nand_gates]

Here I have corrected ur code...
Hope this hepls!

signal ClkBR : std_logic;
signal Counter_BR : INTEGER;

Baud_rate: process
begin
  ClkBR <= '0'; -- 19200 bits per second
  wait for 52 us;
  ClkBR <= '1';
  wait for 52 us;
end process;
--------------------------------------
-- Generate 1MHz clock (1uS)
--------------------------------------

Counter_BR_p : process (ResetNotIn, ClkBR)
begin
  if ResetNotIn = '0' then
    Counter_BR   <= 0;
  elsif rising_edge(ClkBR) then
    if Counter_BR < 20 then
      Counter_BR <= Counter_BR + 1;
    else
      Counter_BR <= 0;
    end if;
  end if;
end process;

read_input : process ()
  file file_in         : text;
  variable line_in     : integer;
  variable buff        : line;
  variable file_opened : boolean := false;
  variable line_in_vec : std_logic_vector(15 downto 0);
  variable Dout_LSByte : std_logic_vector(9 downto 0);
  variable Dout_MSByte : std_logic_vector(9 downto 0);
  variable SDout       : std_logic;
-- function conv_std_logic_vector(line_in: 16:) return std_logic_vector;
begin
  file_open(file_in, "prf_data.txt", read_mode);
  wait until rising_edge(ClkBR);
  while not endfile(file_in) loop
    if Counter_BR = 0 then
-- Read lines until you get an EOF then break out and close file
      readline(file_in, buff);          -- file
      READ(buff, line_in);              -- read integer from file
      line_in_vec := conv_std_logic_vector(line_in, 16);
      Dout_LSByte := STOPBIT & line_in_vec(7 downto 0) & STARTBIT;
      Dout_MSByte := STOPBIT & line_in_vec(15 downto & STARTBIT;
    elsif Counter_BR > 0 and Counter_BR < 20 then
-- shift register for 20 bits of serial data (shift one bit at a time)
      SDout                   := Dout_LSByte(0);  -- shift LSB of LSByte first
      Dout_LSByte(8 downto 0) := Dout_LSByte(9 downto 1);  -- shift LSByte next
      Dout_LSByte(9)          := Dout_MSByte(0);  -- shift LSB of MSByte next
      Dout_MSByte(8 downto 0) := Dout_MSByte(9 downto 1);  -- shift MSByte last
    end if;
  end loop;
end process;

 

[mexico_mike]

If you're reading files, I assume that this is testbench (or non synthesizable) code.
That being the case, why all the code to generate a clock.

signal clk: std_logic := '0'
....


clk <= not clk after time_constant ns;

A lot of coders continue to write synthesizable code when it's not necessary.


Mike