mahaju
Full Member level 2
Hi
I am trying to write a Verilog code to interface computer VGA monitor with an FPGA Board but it is not behaving as I expected it to, and I have no idea why![Oops! :oops: :oops:](data:image/gif;base64,R0lGODlhAQABAIAAAAAAAP///yH5BAEAAAAALAAAAAABAAEAAAIBRAA7)
Please help me
I have attached my code (vga_cont.v) and the test bench(tvga_cont.v) as well as a screen shot of the simulation waveforms from Model Sim
We can see in the figure that the signal H_sync (purple coloured one) goes from 0 to 1 at value 191 of signal cnt11, while I need the signal H_sync to go from 0 to 1 at 190. I think this is what should happen according to my code, but I don't know why it is not happening. Any ideas?
Thanks in advance
:lol:
![](https://obrazki.elektroda.pl/40_1306819027_thumb.jpg)
I am trying to write a Verilog code to interface computer VGA monitor with an FPGA Board but it is not behaving as I expected it to, and I have no idea why
Please help me
I have attached my code (vga_cont.v) and the test bench(tvga_cont.v) as well as a screen shot of the simulation waveforms from Model Sim
We can see in the figure that the signal H_sync (purple coloured one) goes from 0 to 1 at value 191 of signal cnt11, while I need the signal H_sync to go from 0 to 1 at 190. I think this is what should happen according to my code, but I don't know why it is not happening. Any ideas?
Thanks in advance
:lol:
![](https://obrazki.elektroda.pl/40_1306819027_thumb.jpg)