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Need help with my Verilog code

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mahaju

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Hi
I am trying to write a Verilog code to interface computer VGA monitor with an FPGA Board but it is not behaving as I expected it to, and I have no idea why :oops:
Please help me
I have attached my code (vga_cont.v) and the test bench(tvga_cont.v) as well as a screen shot of the simulation waveforms from Model Sim
We can see in the figure that the signal H_sync (purple coloured one) goes from 0 to 1 at value 191 of signal cnt11, while I need the signal H_sync to go from 0 to 1 at 190. I think this is what should happen according to my code, but I don't know why it is not happening. Any ideas?

Thanks in advance
:lol:

 

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FvM

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The code is exactly doing what you have written. All synchronous assigmnents (e.g. register cnt11) are updated at the end of a clock cylce. So H_sync will be set at the same clock edge, when cnt11 advances to 191.
Code:
    cnt11 <= cnt11 + 1;
  end
else if(cnt11 >= 190 && cnt11 <= 1590)
  begin
    H_sync <= 1;
    cnt11 <= cnt11 + 1;
  end
 

mahaju

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Code:
always@(negedge reset_n or posedge clk)
begin
[B].
.
.
.
[/B]// *************** This is the section of code that is related to my problem ***************
		else if(cnt11 >= 0 && cnt11 <= 189) 			
		begin
			H_sync_cyc <= 1;
			H_sync <= 0;
			cnt11 <= cnt11 + 1;
		end
		
		else if(cnt11 >= 190 && cnt11 <= 1590)
		begin
			H_sync <= 1;
			cnt11 <= cnt11 + 1;
		end
// ******************************************************************************************
	end
but since the always@ is working at the posedge of clk, I thought H_sync would change as soon as cnt11 == 190
How can I change this code to get H_sync to go from 0 to 1 at 190 then?
-- EDIT --
Also, does this have anything to do with the characteristics of the non blocking assignment opeartor "<=" ??
 

FvM

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but since the always@ is working at the posedge of clk, I thought H_sync would change as soon as cnt11 == 190
The condition checks the value of cnt11, that has been set in the previous clock cycle. That's how synchronous logic works.
How can I change this code to get H_sync to go from 0 to 1 at 190
All comparing numbers have to be adjusted.
 
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    mahaju

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mahaju

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Ok Solved it
Thank you for your help
 

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