Need help with "expecting ')', found '['" error in

[ikevin]

Hi,

I have a 2-tap FIR filter module as shown below. However, Xilinx kept complaining

ERROR:HDLCompilers:26 - "filter_fir.v" line 6 expecting ')', found '['
ERROR:HDLCompilers:26 - "filter_fir..v" line 7 expecting ')', found '['

The lines that have error are shown in BOLD

module fir_filter (
input reset_b_in,
input system_clock_in,
input [15:0] signal_in,
output [15:0] signal_out,
input [15:0] weight_in [1:0],
output [15:0] weight_out [1:0]
);


reg [15:0] signal_in_after_tap1;
reg [31:0] sum;

assign weight_out = weight_in;
assign signal_out = sum[31:16]; // trucate the least significant 16-bits

always @ (posedge system_clock_in)
begin
if (~reset_b_in)
begin
sum <= 0;
end
else
begin
signal_in_after_tap1 <= signal_in;
sum <= weight_in[0]*signal_in + weight_in[1]*signal_in_after_tap1; // 32 bits
end
end

endmodule

EDITED: added comma.

 

[RBB]

Missing a comma after the line:
output [15:0] signal_out

 

[ikevin]

When I pasted the code, I added bold and messed it up, but the comma is there in the code.

The error still occurs though

 

[RBB]

Maybe you can't pass arrays as inputs/outputs in your Verilog parser?

 

[ikevin]

That's what I've been suspecting... since this is the first time I use multi-dimensional vector in Verilog (with Xilinx)

 

[RBB]

I'm pretty sure that's it.

 

[kalyansumankv]

Re: Need help with "expecting ')', found '['" erro

you are not suppose to use any multi dimentional array's in the input and output oorts

 

[shitansh]

Re: Need help with "expecting ')', found '['" erro

Try this one.......

module fir_filter (
input reset_b_in,
input system_clock_in,
input [15:0] signal_in,
input [15:0] weight_in [1:0],
output [15:0] weight_out [1:0],
output [15:0] signal_out
);


reg [15:0] signal_in_after_tap1;
reg [31:0] sum;


//assign weight_out = weight_in;
assign weight_out [0] [15:0] = weight_in [0] [15:0];
assign weight_out [1] [15:0] = weight_in [1] [15:0];

assign signal_out = sum[31:16]; // trucate the least significant 16-bits

always @ (posedge system_clock_in)
begin
if (~reset_b_in)
begin
sum <= 0;
end
else
begin
signal_in_after_tap1 <= signal_in;
sum <= weight_in[0]*signal_in + weight_in[1]*signal_in_after_tap1; // 32 bits
end
end

endmodule

HTH
--
Shitansh Vaghela

 

[kalyansumankv]

Re: Need help with "expecting ')', found '['" erro

HI shitansh

multi dimentional array's in the input and output list is not acceptable by verilog...

Regards
Kalyan