NEED HELP To SIMULATE VERILOG CODE

[RubyS]

View attachment stimulus1.txtHi am very new to verilog..however i have to submit a code for my assignment and from net i got d code for reed solomon codec.I am using Xilinx 9.2i and MODELSIM SE 6.5 but i m getting Illegal redeclaration of 'inv_gf256' ,Illegal redeclaration of 'gf256mult' in this code..kindly help me asap.

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this is the remaining code ,if i write all of them in d same project d errors r coming

 

[chipseller]

You need to change the modules inv_gf256 and gf256mult to either tasks or functions. Modules are embedded entities in the design and cannot be 'called' in this way. I suspect that you need them to be functions.

View attachment 81041Hi am very new to verilog..however i have to submit a code for my assignment and from net i got d code for reed solomon codec.I am using Xilinx 9.2i and MODELSIM SE 6.5 but i m getting Illegal redeclaration of 'inv_gf256' ,Illegal redeclaration of 'gf256mult' in this code..kindly help me asap.

- - - Updated - - -

this is the remaining code ,if i write all of them in d same project d errors r coming