xabierzu
Newbie
Hi, i am comparing different SRAM cells using the hold, read and write SNM figures. Until now i used to procedure that i read in the book "Robust design and analysis of SRAM", which basically tells you to connect both bitlines (BL and BLB) and wordline (WL) to VDD and add a voltage source connected to one of the storage nodes (Q and QB) and do a parametric analysis. However, i dont know how to simulate the Read SNM for this cell as i have used the same procedure and obtained the same result as in the 6T (which kinda makes sense as the separate read port isn't playing any role by using this procedure). This specific cell should get a much better read snm as it doesnt suffer the disturbances of the writing process. Anyone can help me?
